Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11043491-B2
Application number	US-201916722763-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Feb 10, 2016
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
an n-type field effect transistor (NFET) including a first gate structure; and
a p-type FET (PFET) including a second gate structure, wherein:
the first gate structure includes a first work function adjustment material (WFM) layer disposed directly on a first barrier layer disposed over a first gate dielectric layer,
the second gate structure includes a second WFM layer disposed directly on a second barrier layer disposed over a second gate dielectric layer,
the first WFM layer is a layer of an aluminum containing material, and
the second WFM layer includes a TiN layer disposed on the second barrier layer and a layer of the aluminum containing material disposed over the TiN layer,
the semiconductor device includes a plurality of NFETs having three different threshold voltages and a plurality of PFETs having three different threshold voltages, and
the NFET including the first gate structure has a lowest threshold voltage in an absolute value among the plurality of NFETs, and the PFET including the second gate structure has a lowest threshold voltage in an absolute value among the plurality of PFETs.

2. The semiconductor device of claim 1 , wherein the aluminum containing material is TiAlC.

3. The semiconductor device of claim 2 , wherein:
the first gate structure further includes a first adhesion layer disposed on the first WFM layer and a first metal layer disposed on the first adhesion layer, and
the second gate structure further includes a second adhesion layer disposed on the second WFM layer and a second metal layer disposed on the second adhesion layer.

4. The semiconductor device of claim 3 , wherein:
the first and second adhesion layers include a TiN layer, and
the first and second metal layers include a W layer.

5. The semiconductor device of claim 1 , wherein a thickness of the layer of the aluminum containing material is in a range from 0.5 nm to 10 nm.

6. The semiconductor device of claim 1 , wherein a thickness of the TiN layer in the second WFM layer is 3.5 nm to 8.5 nm.

7. The semiconductor device of claim 1 , wherein the first and second barrier layer includes a TaN layer.

8. A semiconductor device comprising:
an n-type field effect transistor (NFET) including a first gate structure; and
a p-type FET (PFET) including a second gate structure, wherein:
the first gate structure includes a first work function adjustment material (WFM) layer disposed directly on a first barrier layer disposed over a first gate dielectric layer,
the second gate structure includes a second WFM layer disposed directly on a second barrier layer disposed over a second gate dielectric layer,
the first WFM layer includes a first TiN layer disposed on the first barrier layer and a first aluminum containing material layer disposed on the first TiN layer,
the second WFM layer includes a second TiN layer disposed on the second barrier layer and a second aluminum containing material layer disposed on the second TiN layer, and
a thickness of the first TiN layer is smaller than a thickness of the second TiN layer,
the semiconductor device includes a plurality of NFETs having different threshold voltages and a plurality of PFETs having different threshold voltages, and
the NFET including the first gate structure has a highest threshold voltage in an absolute value among the plurality of NFETs, and the PFET including the second gate structure has a highest threshold voltage in an absolute value among the plurality of PFETs.

9. The semiconductor device of claim 8 , wherein the first and second aluminum containing layer is a TiAlC layer.

10. The semiconductor device of claim 9 , wherein:
the first gate structure further includes a first adhesion layer disposed on the first WFM layer and a first metal layer disposed on the first adhesion layer,
the second gate structure further includes a second adhesion layer disposed on the second WFM layer and a second metal layer disposed on the second adhesion layer,
the first and second adhesion layers include a TiN layer, and
the first and second metal layers include a W layer.

11. The semiconductor device of claim 8 , wherein a thickness of the layer of the aluminum containing material is in a range from 0.5 nm to 10 nm.

12. The semiconductor device of claim 8 , wherein a thickness of the first TiN layer is 0.5 nm to 1.2 nm.

13. The semiconductor device of claim 12 , wherein a thickness of the second TiN layer is 2.5 nm to 6 nm.

14. The semiconductor device of claim 8 , wherein the first and second barrier layer includes a TaN layer.

15. A semiconductor device, comprising:
a first p-channel FET including a first gate structure and having a threshold voltage Vp 1 ;
a second p-channel FET including a second gate structure and having a threshold voltage Vp 2 ; and
a third p-channel FET including a third gate structure and having a threshold voltage Vp 3 , wherein:
Vp 1 <Vp 2 <Vp 3 ,
the first gate structure includes a first work function adjustment material (WFM) layer, the second gate structure includes a second WFM layer, and the third gate structure includes a third WFM layer,
at least one of thickness and material of the first to third WFM layers is different from each other,
each of the first, second and third WFM layers includes a first layer made of the first material and a second layer made of a second material different from the first material, and
the first layer is formed over the second layer.

16. The semiconductor device of claim 15 , wherein a thickness of the second layer increases in the order of the first WFM layer, the second WFM layer and the third WFM layer.

17. The semiconductor device of claim 15 , wherein the second material is TiN.

18. The semiconductor device of claim 15 , wherein the first material is TiAlC.

19. The semiconductor device of claim 15 , wherein:
the first, second and third WFM layers are formed over a first conductive layer disposed over a gate dielectric layer, and
a second conductive layer is disposed over each of the first, second and third WFM layers with a third conductive layer interposed therebetween.

20. The semiconductor device of claim 19 , wherein:
the first conductive layer is a TaN layer,
the second conductive layer includes a W layer, and
the third conductive layer includes a TiN layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Shun-Jang
• Liao Chia-Chun
• Wang Shu-Hui
• Chang Shih-Hsun

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title