Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10825813-B2
Application number	US-201816049378-A
Country	US
Kind code	B2
Filing date	Jul 30, 2018
Priority date	Feb 10, 2016
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure, wherein:
the first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET,
the first gate structure includes a first work function adjustment material (WFM) layer disposed on a TaN layer disposed over a gate dielectric layer, and the second gate structure includes a second WFM layer disposed on a TaN layer disposed over a gate dielectric layer, and
at least one of thickness and material of the first and second WFM layers is different from each other,
the first-type-channel FETs further comprises a third first-type-channel FET including a third gate structure,
the third first-type-channel FET has a larger threshold voltage than the second first-type-channel FET,
the third gate structure includes a third WFM layer disposed on a TaN layer disposed over a gate dielectric layer, and
at least one of thickness and material of the first to third WFM layers is different from each other.

2. The semiconductor device of claim 1 , wherein:
the first WFM layer includes a first layer made of a first material,
each of the second and third WFM layers includes a first layer made of the first material and a second layer made of a second material different from the first material, the first layer being formed over the second layer.

3. The semiconductor device of claim 2 , wherein a thickness of the second layer of the second WFM layer is smaller than a thickness of the second layer of the third WFM layer.

4. The semiconductor device of claim 3 , wherein the second material is TiN.

5. The semiconductor device of claim 2 , wherein the first material is TiAlC.

6. The semiconductor device of claim 1 , wherein:
each of the first to third WFM layers includes a layer made a second material, and
a thickness of the layer of the first WFM layer is smaller than a thickness of the layer of the second WFM layer, and the thickness of the layer of the second WFM layer is smaller than a thickness of the layer of the third WFM layer.

7. The semiconductor device of claim 6 , wherein:
each of the first to third WFM layers further includes a layer made a first material, and
the layer made of the first material is formed over the layer of the second material.

8. The semiconductor device of claim 6 , wherein the second material is TiN.

9. A semiconductor device, comprising:
a first n-channel FET including a first gate structure and having a threshold voltage Vn1;
a second n-channel FET including a second gate structure and having a threshold voltage Vn2;
a third n-channel FET including a third gate structure and having a threshold voltage Vn3;
a first p-channel FET including a fourth gate structure and having a threshold voltage Vp1;
a second p-channel FET including a fifth gate structure and having a threshold voltage Vp2; and
a third p-channel FET including a sixth gate structure and having a threshold voltage Vp3, wherein:
Vn1<Vn2<Vn3 and Vp1<Vp2<Vp3,
the first gate structure includes a first work function adjustment material (WFM) layer, the second gate structure includes a second WFM layer, the third gate structure includes a third WFM layer, the fourth gate structure includes a fourth WFM layer, the fifth gate structure includes a fifth WFM layer, and the sixth gate structure includes a sixth WFM layer,
at least one of thickness and material of the first to sixth WFM layers is different from each other,
the first WFM layer includes a first layer made of a first material, and
each of the second to sixth WFM layers includes a first layer made of the first material and a second layer made of a second material different from the first material, the first layer being formed over the second layer.

10. The semiconductor device of claim 9 , wherein a thickness of the second layer increases in the order of the second WFM layer, the third WFM layer, the fourth WFM layer, the fifth WFM layer and the sixth WFM layer.

11. The semiconductor device of claim 10 , wherein the second material is TiN.

12. The semiconductor device of claim 9 , wherein the first material is TiAlC.

13. A semiconductor device, comprising:
a first n-channel FET including a first gate structure and having a threshold voltage Vn1;
a second n-channel FET including a second gate structure and having a threshold voltage Vn2;
a third n-channel FET including a third gate structure and having a threshold voltage Vn3;
a first p-channel FET including a fourth gate structure and having a threshold voltage Vp1;
a second p-channel FET including a fifth gate structure and having a threshold voltage Vp2; and
a third p-channel FET including a sixth gate structure and having a threshold voltage Vp3, wherein:
Vn1<Vn2<Vn3 and Vp1<Vp2<Vp3,
the first gate structure includes a first work function adjustment material (WFM) layer, the second gate structure includes a second WFM layer, the third gate structure includes a third WFM layer, the fourth gate structure includes a fourth WFM layer, the fifth gate structure includes a fifth WFM layer, and the sixth gate structure includes a sixth WFM layer,
at least one of thickness and material of the first to sixth WFM layers is different from each other,
the first to sixth WFM layers are formed over a first conductive layer disposed over a gate dielectric layer, and
a second conductive layer is disposed over each of the first to sixth WFM layers with a third conductive layer interposed therebetween.

14. The semiconductor device of claim 13 , wherein each of first to sixth WFM layers includes a TiAl or TiAlC layer and a TiN layer.

15. The semiconductor device of claim 14 , wherein thicknesses of the TiN layer in the first to sixth WFM layers are different from each other.

16. The semiconductor device of claim 13 , wherein the first conductive layer is a TaN layer.

17. The semiconductor device of claim 13 , wherein the second conductive layer includes W.

18. A semiconductor device comprising:
a first n-channel fin filed effect transistor (FinFET) including a first gate structure; and
a second n-channel FinFET including a second gate structure, wherein:
the first n-channel FinFET has a smaller threshold voltage than the second n-channel FinFET,
the first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer,
the first WFM layer includes a TiAlC layer and a TiN layer disposed on the TiAlC layer,
the second WFM layer includes a first TiN layer, a TiAlC layer disposed on the first TiN layer and a second TiN layer disposed on the TiAlC layer, and
a thickness of the TiN layer of the first WFM layer is equal to a thickness of the second TiN layer of the second WFM.

19. The semiconductor device of claim 18 , further comprising:
a third n-channel FinFET including a third gate structure, wherein:
the third WFM layer includes a third TiN layer, a TiAlC layer disposed on the third TiN layer and a fourth TiN layer disposed on the TiAlC layer, and
a thickness of the first TiN layer of the second WFM layer is different from a thickness of the third TiN layer of the third WFM.

20. The semiconductor device of claim 19 , wherein a thickness of the TiN layer of the first WFM layer is equal to a thickness of the fourth TiN layer of the third WFM layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Shun-Jang
• Liao Chia-Chun
• Wang Shu-Hui
• Chang Shih-Hsun

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title