Semiconductor device including transistors having different threshold voltages

Patent metadata

Field	Value
Publication number	US-9502416-B1
Application number	US-201614990992-A
Country	US
Kind code	B1
Filing date	Jan 8, 2016
Priority date	Jun 4, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first, a second, a third, a fourth areas;
a first, a second, a third, a fourth gate stacks on the first through fourth areas of the substrate, respectively,
wherein the first gate stack includes a first high-dielectric constant (k) layer on the substrate, a first TiN layer on the first high-k layer to contact the first high-k layer and has a first thickness, and a first gate metal on the first TiN layer,
wherein the second gate stack includes a second high-k layer on the substrate, a second TiN layer on the second high-k layer to contact the second high-k layer and has a second thickness, and a second gate metal on the second TiN layer,
wherein the third gate stack includes a third high-k layer on the substrate, a third TiN layer on the third high-k layer to contact the third high-k layer and has a third thickness, and a third gate metal on the third TiN layer, and
wherein the fourth gate stack includes a fourth high-k layer on the substrate, a fourth TiN layer on the fourth high-k layer to contact the fourth high-k layer and has a fourth thickness, and a fourth gate metal on the fourth TiN layer, wherein the first through fourth thicknesses are different.

2. The semiconductor device of claim 1 , wherein:
the first and second areas are n-channel field effect transistor (NFET) areas,
the third and fourth areas are p-channel field effect transistor (PFET) areas, and
the first and second thicknesses are smaller than the third and fourth thicknesses.

3. The semiconductor device of claim 1 , wherein:
the first gate metal includes a first TiAlC layer, a first barrier layer, and a first metal layer,
the second gate metal includes a second TiAlC layer, a second barrier layer, and a second metal layer,
the third gate metal includes a third TiAlC layer, a third barrier layer, and a third metal layer, and
the fourth gate metal includes a fourth TiAlC layer, a fourth barrier layer, and a fourth metal layer.

4. The semiconductor device of claim 3 , wherein the first TiAlC layer contacts the first TiN layer, the second TiAlC layer contacts the second TiN layer, the third TiAlC layer contacts the third TiN layer, and the fourth TiAlC layer contacts the fourth TiN layer.

5. The semiconductor device of claim 4 , wherein the first through fourth gate metals do not includes lanthanum (La) and tantalum nitride (TaN).

6. The semiconductor device of claim 1 , further comprising first through fourth interface layers between the substrate and the first through fourth high-k layers, respectively.

7. The semiconductor device of claim 1 , wherein the first through fourth gate stacks define first through fourth transistors, respectively, the first through fourth transistors having different threshold voltages.

8. The semiconductor device of claim 7 , wherein:
the respective threshold voltages of the first and second transistors in the first and second areas increase as the first and second TiN layers become thicker, and
the respective threshold voltages of the third and fourth transistors in the third and fourth areas decrease as the third and fourth TiN layers become thicker.

9. The semiconductor device of claim 1 , wherein the first through fourth high-k layers extend upward along bottom and sidewalls of the first through fourth metal gate stacks, respectively.

10. A semiconductor device, comprising:
a substrate which includes a low-voltage area and a high-voltage area;
first and third gate stacks on the low-voltage area; and
second and fourth gate stacks on the high-voltage area,
wherein the first gate stack includes a first high-k layer on the substrate, a first TiN layer on the first high-k layer to contact the first high-k layer and has a first thickness, and a first gate metal on the first TiN layer,
wherein the second gate stack includes a second high-k layer on the substrate, a second TiN layer on the second high-k layer to contact the second high-k layer and has a second thickness greater than the first thickness, and a second gate metal on the second TiN layer,
wherein the third gate stack includes a third high-k layer on the substrate, a third TiN layer on the third high-k layer to contact the third high-k layer and has a third thickness greater than the second thickness, and a third gate metal on the third TiN layer, and
wherein the fourth gate stack includes a fourth high-k layer on the substrate, a fourth TiN layer on the fourth high-k layer to contact the fourth high-k layer and has a fourth thickness greater than the second thickness and smaller than the third thickness, and a fourth gate metal on the fourth TiN layer.

11. The semiconductor device of claim 10 , wherein:
the first gate metal includes a first TiAlC layer, a first barrier layer, and a first metal layer,
the second gate metal includes a second TiAlC layer, a second barrier layer, and a second metal layer,
the third gate metal includes a third TiAlC layer, a third barrier layer, and a third metal layer, and
the fourth gate metal includes a fourth TiAlC layer, a fourth barrier layer, and a fourth metal layer.

12. The semiconductor device of claim 11 , wherein the first TiAlC layer contacts the first TiN layer, the second TiAlC layer contacts the second TiN layer, the third TiAlC layer contacts the third TiN layer, and the fourth TiAlC layer contacts the fourth TiN layer.

13. The semiconductor device of claim 12 , wherein the first through fourth gate metals do not includes lanthanum (La) and tantalum nitride (TaN).

14. The semiconductor device of claim 10 , wherein:
the first through fourth gate stacks define first through fourth transistors having different threshold voltages, respectively,
the first and second transistors are n-channel field effect transistor (NFET), and
the second and fourth transistors are p-channel field effect transistor (PFET).

15. The semiconductor device of claim 14 , wherein:
the respective threshold voltages of the first and second transistors increase as the first and second TiN layers become thicker, and
the respective threshold voltages of the third and fourth transistors decrease as the third and fourth TiN layers become thicker.

16. A semiconductor device, comprising:
a first through fourth transistors, wherein:
the first transistor includes a first interface layer, a first high-k layer on the first interface layer, a first TiN layer on the first high-k layer to contact the first high-k layer and has a first thickness, and a first gate metal on the first TiN layer,
the second transistor includes a second interface layer, a second high-k layer on the second interface layer, a second TiN layer on the second high-k layer to contact the second high-k layer and has a second thickness greater than the first thickness, and a second gate metal on the second TiN layer,
the third transistor includes a third interface layer, a third high-k layer on the third interface layer, a third TiN layer on the third high-k layer to contact the third high-k layer and has a third thickness greater than the second thickness, and a third gate metal on the third TiN layer, and
the fourth transistor includes a fourth interface layer, a fourth high-k layer on the fourth interface layer, a fourth TiN layer on the fourth high-k layer to contact the fourth high-k layer and has a fourth thickness greater than the second thickness and smaller than the third thickness, and a fourth gate metal on the fourth TiN layer, and
the first through fourth gate metals do not include lanthanum (La) and tantalum nitride (TaN).

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ju-Youn

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/6548

  by forming intermediate materials, e.g. capping layers or diffusion barriers · CPC title

• H10P14/6519

  the substance being oxygen · CPC title

• H10P14/6506

  Formation of intermediate materials · CPC title