Display substrate, display device, and manufacturing method of display substrate

Patent metadata

Field	Value
Publication number	US-12165597-B2
Application number	US-202218020971-A
Country	US
Kind code	B2
Filing date	Jan 29, 2022
Priority date	Jan 29, 2022
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a gate driving circuit including shift register units and clock signal lines including a first clock signal line, a second clock signal line providing a second clock signal, and a third clock signal line providing a third clock signal. An input circuit of a n-th stage shift register unit in the shift register units is connected with the first clock signal line, a first control circuit of the n-th stage shift register unit is connected with the first clock signal line, the second clock signal line, and the third clock signal line, a second control circuit of the n-th stage shift register unit is connected with the second clock signal line, and a phase of the second clock signal is opposite to a phase of the third clock signal.

First claim

What is claimed is:

1. A display substrate, comprising: a base substrate, and a gate driving circuit and a plurality of clock signal lines arranged on the base substrate,
wherein the gate driving circuit comprises a plurality of shift register units,
each shift register unit comprises an input circuit, a first control circuit, a second control circuit, an output circuit, a trigger terminal, and an output terminal,
the input circuit is electrically connected with the trigger terminal and a first node respectively and receives a first control signal, and is configured to input a trigger signal received by the trigger terminal to the first node under control of the first control signal;
the first control circuit is electrically connected with the first node, a second node, and a first output node respectively and receives the first control signal, a second control signal, and a third control signal, and is configured to write a first output control signal into the first output node under control of the first control signal, a voltage of the first node, and the second control signal, wherein the first output control signal comprises the third control signal;
the second control circuit is electrically connected with the first node, the second node, and a second output node respectively and receives the second control signal, and is configured to write a second output control signal into the second output node under control of the second control signal and a voltage of the second node;
the output circuit is electrically connected with a first voltage line, a second voltage line, the first output node, the second output node, and the output terminal respectively, and is configured to write a first voltage signal provided by the first voltage line or a second voltage signal provided by the second voltage line into the output terminal as an output signal under control of the first output control signal and the second output control signal;
the plurality of clock signal lines comprise a first clock signal line, a second clock signal line, and a third clock signal line,
the first clock signal line is configured to provide a first clock signal, the second clock signal line is configured to provide a second clock signal, and the third clock signal line is configured to provide a third clock signal,
the plurality of shift register units comprise an n-th stage shift register unit, and n is a positive integer,
an input circuit of the n-th stage shift register unit is connected with the first clock signal line to receive the first clock signal as the first control signal,
a first control circuit of the n-th stage shift register unit is connected with the first clock signal line, the second clock signal line, and the third clock signal line to receive the first clock signal as the first control signal, to receive the second clock signal as the second control signal, and to receive the third clock signal as the third control signal,
a second control circuit of the n-th stage shift register unit is connected with the second clock signal line to receive the second clock signal as the second control signal, and
a phase of the second clock signal is opposite to a phase of the third clock signal.

2. The display substrate according to claim 1 , wherein on the base substrate, the first clock signal line, the second clock signal line, and the third clock signal line extend in a first direction and are arranged in a second direction different from the first direction.

3. The display substrate according to claim 2 , wherein in the second direction, the first clock signal line, the third clock signal line, and the second clock signal line are sequentially arranged;
wherein on the base substrate, the first voltage line and the second voltage line extend in the first direction and are arranged in the second direction; and
wherein in the second direction, the first voltage line is between the third clock signal line and the second clock signal line, and the first clock signal line and the third clock signal line are between the first voltage line and the second voltage line.

4. The display substrate according to claim 2 , wherein each shift register unit comprises at least one first transistor, and at least one first transistor in the n-th stage shift register unit is electrically connected with the second clock signal line to be turned on or off under control of the second clock signal;
wherein the at least one first transistor is an oxide transistor.

5. The display substrate according to claim 4 , wherein each shift register unit further comprises a plurality of second transistors, a type of at least one active layer of the at least one first transistor is different from types of active layers of the plurality of second transistors,
the at least one active layer of the at least one first transistor is located in a same layer, and the active layers of the plurality of second transistors are located in a same layer,
a layer where the at least one active layer of the at least one first transistor is located is different from a layer where the active layers of the plurality of second transistors are located;
wherein the plurality of second transistors are polysilicon transistors;
wherein an orthographic projection of the at least one active layer of the at least one first transistor on the base substrate does not overlap with an orthographic projection of the active layers of the plurality of second transistors on the base substrate;
wherein at least one gate electrode of the at least one first transistor is located in a same layer, and gate electrodes of the plurality of second transistors are located in a same layer,
a layer where the at least one gate electrode of the at least one first transistor is located is different from a layer where the gate electrodes of the plurality of second transistors are located.

6. The display substrate according to claim 4 , further comprising at least one gate connection line corresponding to the at least one first transistor one by one and a plurality of holes,
wherein the plurality of holes comprise at least one first hole corresponding to each gate connection line,
for each first transistor: a gate electrode of the first transistor in the n-th stage shift register unit is electrically connected with a gate connection line corresponding to the first transistor, and the gate connection line corresponding to the first transistor extends to the second clock signal line approximately along the second direction and is electrically connected with the second clock signal line through at least one first hole corresponding to the gate connection line;
wherein the gate electrode of the first transistor is integrally provided with the gate connection line corresponding to the first transistor;
wherein an orthographic projection of each gate connection line on the base substrate does not overlap with an orthographic projection of holes other than the first hole in the plurality of holes on the base substrate.

7. The display substrate according to claim 5 , further comprising a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, an oxide layer, a fourth insulating layer, a third metal layer, a fifth insulating layer, and a fourth metal layer, which are successively stacked on the base substrate;
wherein the semiconductor layer is on the base substrate, the first insulating layer is on a side of the semiconductor layer away from the base substrate, the first metal layer is on a side of the first insulating layer away from the semiconductor layer, the second insulating layer is on a side of the first metal layer away from the first insulating layer, the second metal layer is

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Chen Yipeng
• Lu Hui
• Shi Ling

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/425

  having different crystal properties in different TFTs or within an individual TFT · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title