Shift register unit, gate drive circuit and display device

Patent metadata

Field	Value
Publication number	US-10997936-B2
Application number	US-201916475473-A
Country	US
Kind code	B2
Filing date	Jan 10, 2019
Priority date	Apr 28, 2018
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A shift register unit, a gate drive circuit and a display device are disclosed. The shift register unit includes an input circuit, an output circuit, a reset circuit, a control circuit and a reset stabilizing circuit. The input circuit is configured to write an input signal into a first node in response to an input start signal. The output circuit is configured to output a preparatory output signal to an output terminal under control of an electric level of the first node. The reset circuit is configured to reset the output terminal under control of an electric level of a second node. The control circuit is configured to apply a first voltage signal to the second node in response to a control signal. The reset stabilizing circuit is configured to apply a second voltage signal to the first node in response to a reset stabilizing signal.

First claim

What is claimed is:

1. A shift register unit, comprising: an input circuit, an output circuit, a reset circuit, a control circuit and a reset stabilizing circuit, wherein the input circuit is configured to write an input signal into a first node in response to an input start signal; the output circuit is configured to output a preparatory output signal to an output terminal under control of an electric level of the first node; the reset circuit is configured to reset the output terminal under control of an electric level of a second node; the control circuit is configured to apply a first voltage signal to the second node in response to a control signal; and the reset stabilizing circuit is configured to apply a second voltage signal to the first node in response to a reset stabilizing signal; further comprising an output stabilizing circuit, wherein the output stabilizing circuit is configured to be switched on or off, according to a change in an electrical level of a signal outputted by the output terminal, under control of the first voltage signal.

2. The shift register unit according to claim 1 , wherein the reset stabilizing circuit comprises a first transistor and a second transistor, and the reset stabilizing signal comprises a first reset stabilizing signal and a second reset stabilizing signal;
a gate electrode of the first transistor is configured to be connected with the second node to take the electric level of the second node as the first reset stabilizing signal, a first terminal of the first transistor is configured to be connected with a first clock signal line to receive a first clock signal as the second reset stabilizing signal, and a second terminal of the first transistor is configured to be connected with a gate electrode of the second transistor; and
a first terminal of the second transistor is configured to be connected with a second voltage terminal to receive the second voltage signal, and a second terminal of the second transistor is configured to be connected with the first node.

3. The shift register unit according to claim 1 , wherein the reset stabilizing circuit comprises a third transistor and a fourth transistor, and the reset stabilizing signal comprises a first reset stabilizing signal and a second reset stabilizing signal;
a gate electrode of the third transistor is configured to be connected with the second node to take the electric level of the second node as the first reset stabilizing signal, a first terminal of the third transistor is configured to be connected with a second voltage terminal to receive the second voltage signal, and a second terminal of the third transistor is configured to be connected with a first terminal of the fourth transistor; and
a gate electrode of the fourth transistor is configured to be connected with a first clock signal line to receive a first clock signal as the second reset stabilizing signal, and a second terminal of the fourth transistor is configured to be connected with the first node.

4. The shift register unit according to claim 1 , wherein the input circuit comprises a fifth transistor; and
a gate electrode of the fifth transistor is configured to be connected with a second clock signal line to receive a second clock signal as the input start signal, a first terminal of the fifth transistor is configured to be connected with an input signal line to receive the input signal, and a second terminal of the fifth transistor is configured to be connected with the first node.

5. The shift register unit according to claim 1 , wherein the output circuit comprises a sixth transistor and a first capacitor;
a gate electrode of the sixth transistor is configured to be connected with the first node, a first terminal of the sixth transistor is configured to be connected with a first clock signal line to receive a first clock signal as the preparatory output signal, and a second terminal of the sixth transistor is taken as the output terminal; and
a first electrode of the first capacitor is configured to be connected with the gate electrode of the sixth transistor, and a second electrode of the first capacitor is configured to be connected with the second terminal of the sixth transistor.

6. The shift register unit according to claim 1 , wherein the reset circuit comprises a seventh transistor and a second capacitor;
a gate electrode of the seventh transistor is configured to be connected with the second node, a first terminal of the seventh transistor is configured to be connected with a second voltage terminal to receive the second voltage signal, and a second terminal of the seventh transistor is configured to be connected with the output terminal; and
a first electrode of the second capacitor is configured to be connected with the gate electrode of the seventh transistor, and a second electrode of the second capacitor is configured to be connected with the first terminal of the seventh transistor.

7. The shift register unit according to claim 1 , wherein the control circuit comprises an eighth transistor and a ninth transistor, and the control signal comprises a first control signal and a second control signal;
a gate electrode of the eighth transistor is configured to be connected with a second clock signal line to receive a second clock signal as the first control signal, a first terminal of the eighth transistor is configured to be connected with a first voltage terminal to receive the first voltage signal, and a second terminal of the eighth transistor is configured to be connected with the second node; and
a gate electrode of the ninth transistor is configured to be connected with the input circuit to receive the input signal inputted from the input circuit and take the input signal as the second control signal, a first terminal of the ninth transistor is configured to be connected with the second clock signal line to receive the second clock signal, and a second terminal of the ninth transistor is configured to be connected with the second terminal of the eighth transistor.

8. The shift register unit according to claim 1 , wherein the output stabilizing circuit comprises a tenth transistor; and a gate electrode of the tenth transistor is configured to be connected with a first voltage terminal to receive the first voltage signal, a first terminal of the tenth transistor is configured to be connected with the input circuit and the reset stabilizing circuit, and a second terminal of the tenth transistor is configured to be connected with the first node.

9. The shift register unit according to claim 1 , wherein transistors of the shift register unit are P-type transistors, and a material of an active layer of each of the P-type transistors comprises low-temperature polysilicon.

10. The shift register unit according to claim 1 , further comprising an output stabilizing circuit,
wherein the output stabilizing circuit comprises an output stabilizing transistor, a gate electrode of the output stabilizing transistor is configured to be connected with a second voltage terminal to receive the second voltage signal, a first terminal of the output stabilizing transistor is configured to be connected with the input circuit and the reset stabilizing circuit, and a second terminal of the output stabilizing transistor is configured to be connected with the first node; and
the output stabilizing transistor is an N-type transistor, and a material of an active layer of the N-type transistor comprises an oxide; and
transistors, except for the output stabilizing transistor, of the shift register unit are P-type transistors; and a material of an active layer of each of the P-type transistors comprises low-temperature polysilicon.

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Assignees

• Boe Technology Group Co Ltd

Inventors

• Xu Chen
• Hao Xueguang
• Qiao Yong
• Wu Xinyin

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/36 Primary

  using liquid crystals · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title