Shift register unit, method of driving shift register unit, gate drive circuit, and display device

Patent metadata

Field	Value
Publication number	US-11335293-B2
Application number	US-201916491910-A
Country	US
Kind code	B2
Filing date	Feb 18, 2019
Priority date	Jun 21, 2018
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

A shift register unit, a method of driving a shift register unit, a gate drive circuit, and a display device are provided. The shift register unit includes an input circuit, an output circuit, a first reset circuit, and a reset control circuit. The input circuit is configured to control a level of a first node; the output circuit is configured to output a clock signal to an output terminal; the first reset circuit is configured to reset the first node; and the reset control circuit is configured to input the first reset signal to the first reset circuit in response to a reset control signal and a reference signal, to turn on the first reset circuit and the reset control circuit is further configured to enable an amplitude of a level of the first reset signal to be larger than an amplitude of a level of the reference signal.

First claim

What is claimed is:

1. A shift register unit, comprising an input circuit, an output circuit, a first reset circuit, and a reset control circuit,
wherein the input circuit is connected to a first node, and the input circuit is configured to control a level of the first node in response to an input signal;
the output circuit is connected to the first node and an output terminal, and the output circuit is configured to output a clock signal to the output terminal under control of the level of the first node;
the first reset circuit is connected to the first node, and the first reset circuit is configured to reset the first node in response to a first reset signal; and
the reset control circuit is connected to the first reset circuit, the reset control circuit is configured to, in response to a reset control signal and a reference signal, input the first reset signal to the first reset circuit to turn on the first reset circuit, and the reset control circuit is further configured to enable an amplitude of a level of the first reset signal to be larger than an amplitude of a level of the reference signal,
wherein the reset control circuit comprises:
a drive sub-circuit, connected to a reset control node, and configured to adjust a level of the reset control node according to the reset control signal and the reference signal, and the level of the reset control node is used as the first reset signal; and
a reset sub-circuit, connected to the reset control node, and configured to reset the reset control node and the drive sub-circuit in response to a reset sub-signal,
wherein the drive sub-circuit comprises a first capacitor and a first transistor, a first electrode of the first capacitor is connected to a reset control signal terminal to receive the reset control signal, a second electrode of the first capacitor is connected to a reference signal terminal to receive the reference signal, a gate electrode of the first transistor is connected to the first electrode of the first capacitor, a first electrode of the first transistor is connected to the second electrode of the first capacitor, and a second electrode of the first transistor is connected to the reset control node; and
the reset sub-circuit comprises a second transistor and a third transistor, a gate electrode of the second transistor is connected to a reset sub-signal terminal to receive the reset sub-signal, a first electrode of the second transistor is connected to the gate electrode of the first transistor, a second electrode of the second transistor is connected to a first voltage terminal to receive a first voltage, a gate electrode of the third transistor is connected to the reset sub-signal terminal to receive the reset sub-signal, a first electrode of the third transistor is connected to the reset control node, and a second electrode of the third transistor is connected to the first voltage terminal.

2. The shift register unit according to claim 1 , wherein the reference signal terminal is connected to a clock signal terminal to receive the clock signal as the reference signal.

3. The shift register unit according to claim 1 , further comprising a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, a first node noise reduction circuit, and an output noise reduction circuit,
wherein the first control circuit is connected to a second node, the first node, and a first control node, and the first control circuit is configured to control a level of the second node under control of the level of the first node and a level of the first control node;
the second control circuit is connected to a third node, the first node, and a second control node, and the second control circuit is configured to control a level of the third node under control of the level of the first node and a level of the second control node;
the third control circuit is connected to the first control node and the first node, and the third control circuit is configured to control the level of the first control node under control of the level of the first node;
the fourth control circuit is connected to the second control node and the first node, and the fourth control circuit is configured to control the level of the second control node under control of the level of the first node;
the first node noise reduction circuit is connected to the first node, the second node, and the third node, and the first node noise reduction circuit is configured to perform noise reduction on the first node under control of the level of the second node or the level of the third node; and
the output noise reduction circuit is connected to the output terminal, the second node, and the third node, and the output noise reduction circuit is configured to perform noise reduction on the output terminal under control of the level of the second node or the level of the third node.

4. The shift register unit according to claim 3 , wherein the input circuit comprises a fourth transistor,
a gate electrode of the fourth transistor is connected to a first electrode of the fourth transistor and is connected to an input terminal to receive the input signal, and a second electrode of the fourth transistor is connected to the first node.

5. The shift register unit according to claim 3 , wherein the output terminal of the output circuit comprises at least one shift signal output terminal and at least one pixel signal output terminal.

6. The shift register unit according to claim 5 , wherein the output circuit comprises a fifth transistor, a sixth transistor, and a second capacitor;
a gate electrode of the fifth transistor is connected to the first node, a first electrode of the fifth transistor is connected to a clock signal terminal to receive the clock signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal;
a gate electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to the clock signal terminal to receive the clock signal, and a second electrode of the sixth transistor is connected to the pixel signal output terminal; and
a first electrode of the second capacitor is connected to the first node, and a second electrode of the second capacitor is connected to the second electrode of the sixth transistor or the second electrode of the fifth transistor.

7. The shift register unit according to claim 5 , wherein the output noise reduction circuit comprises an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twenty-first transistor;
a gate electrode of the eighteenth transistor is connected to the second node, a first electrode of the eighteenth transistor is connected to the shift signal output terminal, and a second electrode of the eighteenth transistor is connected to a first voltage terminal to receive a first voltage;
a gate electrode of the nineteenth transistor is connected to the third node, a first electrode of the nineteenth transistor is connected to the shift signal output terminal, and a second electrode of the nineteenth transistor is connected to the first voltage terminal;
a gate electrode of the twentieth transistor is connected to the second node, a first electrode of the twentieth transistor is connected to the pixel signal output terminal, and a second electrode of the twentieth transistor is connected to a fourth voltage terminal to receive a fourth voltage; and
a gate electrode of the twenty-first transistor is connected to the third node, a first electrode of the twenty-first transistor is connected to the pixel signal output terminal, and a second electrode of the twenty-first transistor is connected to the fourth voltage terminal.

8. The shift regi

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Xie Yongxian
• Zou Yifeng
• Wang Hui
• Zheng Mindong

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title