GOA unit and method for driving the same, GOA circuit and display device

Patent metadata

Field	Value
Publication number	US-9721674-B2
Application number	US-201514801719-A
Country	US
Kind code	B2
Filing date	Jul 16, 2015
Priority date	Oct 31, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Embodiments of the present disclosure provide a GOA unit and a method for driving the same, a GOA circuit and a display device. The embodiments of the preset disclosure relate in particular to the field of display manufacture. The GOA unit specifically comprises: a first node control module and a second node control module, wherein the first node control module is connected to a first control node, an input signal terminal, a first clock signal terminal, and an output signal terminal, wherein the second node control module is connected to a reset signal terminal, a second clock signal terminal, a third clock signal terminal, a first level terminal, the output terminal, and the first control node. The embodiment of the present disclosure may simplify the structure of a GOA circuit and be used for display manufacture.

First claim

I claim:

1. A GOA unit, comprising a first node control module and a second node control module,
wherein the first node control module is connected to a first control node, an input signal terminal, a first clock signal terminal, and an output signal terminal, and the first node control module is configured to, under the control of an input signal from the input signal terminal, pull a voltage of the first control node to be equal to a voltage of the input signal from the input signal terminal, and further configured to, under the control of the first control node, output via the output signal terminal a first clock signal from the first clock signal terminal, and
wherein the second node control module is connected to a reset signal terminal, a second clock signal terminal, a third clock signal terminal, a first level terminal, the output signal terminal, and the first control node, and the second node control module is configured to, under the control of a reset signal of the reset signal terminal and a second clock signal of the second clock signal terminal, pull the voltage of the first control node to be equal to a first voltage of the first level terminal, and further configured to, under the control of the first control node, a second clock signal from the second clock signal terminal, and a third clock signal from the third clock signal terminal, pull a voltage of the output signal terminal to be equal to the first voltage of the first level terminal;
wherein the second node control module comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, and
wherein the third transistor has a gate connected to a first terminal of the third transistor, the first terminal of the third transistor being connected to the second clock signal terminal and a second terminal of the third transistor being connected to a first terminal of the fourth transistor,
wherein the fourth transistor has a gate connected to the first control node, a second terminal of the fourth transistor being connected the first level terminal,
wherein the fifth transistor has a gate connected to the second terminal of the third transistor, a first terminal of the fifth transistor being connected to the first control node and a second terminal of the fifth transistor being connected to the first level terminal,
wherein the sixth transistor has a gate connected to the second terminal of the third transistor, a first terminal of the sixth transistor being connected to the output signal terminal and a second terminal of the sixth transistor being connected to the first level terminal,
wherein the seventh transistor has a gate connected to the third clock signal terminal, a first terminal of the seventh transistor being connected to the output signal terminal and a second terminal of the seventh transistor being connected to the first level terminal, and
wherein the eighth transistor has a gate connected to the reset signal terminal, a first terminal of the eighth transistor being connected to the first control node and a second terminal of the eighth transistor being connected to the first level terminal.

2. The GOA unit according to claim 1 , wherein the first node control module comprises a first transistor, a second transistor, and a first capacitor, and
wherein the first transistor has a gate connected to a first terminal of the first transistor, the first terminal of the first transistor being connected to the input signal terminal and a second terminal of the first transistor being connected to the first control node,
wherein the second transistor has a gate connected to the first control node, a first terminal of the second transistor being connected to the first clock signal terminal and a second terminal of the second transistor being connected to the output signal terminal, and
wherein the first capacitor has a first plate connected to the first control node and a second plate connected to the output signal terminal.

3. The GOA unit according to claim 1 , wherein the second node control module is further connected to the first clock signal terminal, and wherein the second node control module further comprises a ninth transistor,
wherein the ninth transistor has a gate connected to a first terminal of the ninth transistor, the first terminal of the ninth transistor being connected to the first clock signal terminal and a second terminal of the ninth transistor being connected to the second terminal of the third transistor.

4. The GOA unit according to claim 1 , wherein the second node control module is further connected to the first clock signal terminal, and wherein the second node control module further comprises a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor,
wherein the ninth transistor has a gate connected to a first terminal of the ninth transistor, the first terminal of the ninth transistor being connected to the first clock signal terminal and a second terminal of the ninth transistor being connected to a first terminal of the tenth transistor,
wherein the tenth transistor has a gate connected to the first control node, the first terminal of the tenth transistor being connected to a gate of the eleventh transistor and a second terminal of the tenth transistor being connected to the first level terminal,
wherein the eleventh transistor has a gate connected to a gate of the twelfth transistor, a first terminal of the eleventh transistor being connected to the first control node and a second terminal of the eleventh transistor being connected to the first level terminal, and
wherein the twelfth transistor has a first terminal connected to the output signal terminal and a second terminal connected to the first level terminal.

5. A GOA circuit, comprising at least one GOA unit according to claim 1 .

6. The GOA circuit according to claim 5 , wherein the GOA circuit comprises at least two cascaded GOA units which are referred to as the 1 st stage GOA unit, the 2 nd stage GOA unit, . . . , the n th stage GOA unit,
wherein the 1 st stage GOA unit has an input signal terminal connected to a frame initial signal terminal which inputs a first frame initial signal, and the 1 st stage GOA unit has a reset signal terminal connected to an output signal terminal of the 2 nd stage GOA unit,
wherein the m th stage GOA. unit has an input signal terminal connected to an output signal terminal of the m−1 th stage GOA unit, and the m th stage GOA unit has a reset signal terminal connected to an output signal terminal of the m+1 th stage GOA unit, and
wherein the n th stage GOA unit has a reset signal terminal connected to the frame initial signal terminal,
where n is a positive integer equal to or greater than 2 and m={2, . . . , n−1}.

7. The GOA circuit according to claim 5 , wherein the GOA circuit comprises at least three cascaded GOA units, which are referred to as the 1 st stage GOA unit, the 2 nd stage GOA unit, . . . , the n th stage GOA unit,
wherein the 1 st stage GOA unit has an input signal terminal connected to a frame initial signal terminal which inputs a first frame initial signal, and the 1 st stage GOA unit has a reset signal terminal connected to an output signal terminal of the 3 rd stage GOA unit,
wherein the k th stage GOA unit has an input signal terminal connected to an output signal terminal of the k−1 th stage GOA unit, and the k th stage GOA unit has a reset signal terminal connected to an output signal terminal of the k+2 th stage GOA unit, and
wherein the n−1 th stage GOA unit has a reset signal terminal connected to the frame initial signal terminal and the n th stage GOA unit has a reset signal terminal connected to the frame initi

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Gu Xiaofang

Classifications

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title