Shift register, driving method thereof, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-10186221-B2
Application number	US-201615512284-A
Country	US
Kind code	B2
Filing date	Feb 19, 2016
Priority date	Sep 28, 2015
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A shift register, a driving method, a gate driving circuit and a display device are disclosed. The input module controls the potential of the first node. The first reset module controls the potential of the first node. The second reset module controls the potential of the driving signal output terminal. The first output module controls the potential of the driving signal output terminal under the control of the first node. The second output module controls the potential of the driving signal output terminal under the control of the second node. The pull-down driving module controls the potentials of the first node and the second node. Since the node control signal at the node control signal terminal can eliminate the noise on the first node resulting from the change in the first clock signal, the output stability of the shift register can be improved.

First claim

The invention claimed is:

1. A shift register comprising: an input module, a first reset module, a second reset module, a first output module, a second output module and a pull-down driving module; wherein
a first terminal of the input module is connected to an input signal terminal, a second terminal of the input module is connected to a first node; the input module is configured to control a potential of the first node under the control of the input signal terminal;
a first terminal of the first reset module is connected to a reference signal terminal, a second terminal of the first reset module is connected to a first reset control signal terminal, a third terminal of the first reset module is connected to the first node; the first reset module is configured to provide a reference signal of the reference signal terminal to the first node under the control of the first reset control signal terminal;
a first terminal of the second reset module is connected to a second reset control signal terminal, a second terminal of the second reset module is connected to the reference signal terminal, a third terminal of the second reset module is connected to a driving signal output terminal; the second reset module is configured to provide the reference signal to the driving signal output terminal under the control of the second reset control signal terminal;

a first terminal of the first output module is connected to a first clock signal terminal for receiving a first clock signal, a second terminal of the first output module is connected to the first node, a third terminal of the first output module is connected to the driving signal output terminal; the first output module is configured to provide the first clock signal of the first clock signal terminal to the driving signal
output terminal under the control of the first node;
a first terminal of the second output module is connected to the reference signal terminal, a second terminal of the second output module is connected to a second node, a third terminal of the second output module is connected to the driving signal output terminal; the second output module is configured to provide the reference signal to the driving signal output terminal under the control of the second node;
a first terminal of the pull-down driving module is connected to a node control signal terminal, a second terminal of the pull-down driving module is connected to the reference signal terminal, a third terminal of the pull-down driving module is connected to the first node, a fourth terminal of the pull-down driving module is connected to the second node; the pull-down driving module is configured to control a potential of the second node to be a second potential when the potential of the first node is a first potential, and control the potential of the first node to be the second potential when the potential of the second node is the first potential;
when an effective pulse signal of the input signal terminal is a high-potential signal, the first potential is a high potential and the second potential is a low potential; when the effective pulse signal of the input signal terminal is a low-potential signal, the first potential is a low potential and the second potential is a high potential; a node control signal of the node control signal terminal is configured to eliminate a noise on the first node resulting from change in the first clock signal
wherein the pull-down driving module further comprises a fifth terminal connected to the input signal terminal, a sixth terminal connected to the driving signal output terminal, and a seventh terminal connected to a third clock signal terminal for receiving a third clock signal,
wherein the pull-down driving module comprises a sixth switch transistor, a seventh switch transistor, an eighth switch transistor, an eleventh switch transistor, a twelfth switch transistor, a thirteenth switch transistor, a fourteenth switch transistor and a fifteenth switch transistor; wherein
a gate and a source of the sixth switch transistor are both connected to the node control signal terminal, a drain of the sixth switch transistor is connected to a gate of the seventh switch transistor, a source of the eleventh switch transistor and a source of the twelfth switch transistor, respectively;
a source of the seventh switch transistor is connected to the node control signal terminal, a drain of the seventh switch transistor is connected to the second node;
a gate of the eighth switch transistor is connected to the second node, a source of the eighth switch transistor is connected to the first node, a drain of the eighth switch transistor is connected to the reference signal terminal;
a gate of the eleventh switch transistor is connected to the driving signal output terminal, a drain of the eleventh switch transistor is connected to the reference signal terminal;
a gate of the twelfth switch transistor is connected to the input signal terminal and a drain of the twelfth switch transistor is connected to the reference signal terminal;
a gate of the thirteenth switch transistor is connected to the input signal terminal, a source of the thirteenth switch transistor is connected to the second node, a drain of the thirteenth switch transistor is connected to the reference signal terminal;
a gate of the fourteenth switch transistor is connected to the driving signal output terminal, a source of the fourteenth switch transistor is connected to the second node, a drain of the fourteenth switch transistor is connected to the reference signal terminal;
a gate of the fifteenth switch transistor is connected to the third clock signal terminal, a source of the fifteenth switch transistor is connected to the driving signal output terminal, a drain of the fifteenth switch transistor is connected to the reference signal terminal,
wherein the node control signal is a second clock signal, and a duty cycle of the second clock signal is 2% to 50%;
wherein the third clock signal has a phase opposite to the first clock signal; and
wherein the second clock signal is different from the first and third clock signals.

2. A gate driving circuit comprising a plurality of cascaded shift registers, each shift register comprising an input module, a first reset module, a second reset module, a first output module, a second output module and a pull-down driving module; wherein
a first terminal of the input module is connected to an input signal terminal, a second terminal of the input module is connected to a first node; the input module is configured to control a potential of the first node under the control of the input signal terminal;
a first terminal of the first reset module is connected to a reference signal terminal, a second terminal of the first reset module is connected to a first reset control signal terminal, a third terminal of the first reset module is connected to the first node; the first reset module is configured to provide a reference signal of the reference signal terminal to the first node under the control of the first reset control signal terminal;
a first terminal of the second reset module is connected to a second reset control signal terminal, a second terminal of the second reset module is connected to the reference signal terminal, a third terminal of the second reset module is connected to a driving signal output terminal; the second reset module is configured to provide the reference signal to the driving signal output terminal under the control of the second reset control signal terminal for receiving a first clock signal;
a first terminal of the first output module is connected to a first clock signal terminal, a second terminal of the first output module is connected to the first node, a third terminal of the first output module is connected to the driving signal output terminal; the first output module is conf

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shang Guangliang
• Zheng Haoliang

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/36

  using liquid crystals · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C8/04

  using a sequential addressing device, e.g. shift register, counter · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title