Semiconductor device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-12160992-B2
Application number	US-202117563547-A
Country	US
Kind code	B2
Filing date	Dec 28, 2021
Priority date	May 26, 2021
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

A semiconductor device includes a substrate having a cell region and a connection region, a first stack structure with a plurality of first gate layers and a plurality of first interlayer insulating layers, and a second stack structure with a plurality of second gate layers and a plurality of second interlayer insulating layers. Each of the first gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. Each of the second gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. A thickness difference between the end and central portions of each first gate layer is different from a thickness difference between the end and central portions of each second gate layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a cell region and a connection region;
a first stack structure including first gate layers and first interlayer insulating layers, the first gate layers being stacked on the substrate alternately with the first interlayer insulating layers one by one in a vertical direction; and
a second stack structure including second gate layers and second interlayer insulating layers, the second gate layers being stacked on the first stack structure alternately with the second interlayer insulating layers one by one in the vertical direction,
wherein each of the first gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate,
wherein each of the second gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate, and
wherein a first difference between a thickness in the vertical direction of the end portion of each of at least two of the first gate layers and a thickness in the vertical direction of the central portion of each of the at least two of the first gate layers is different from a second difference between a thickness in the vertical direction of the end portion of each of at least two of the second gate layers and a thickness in the vertical direction of the central portion of each of the at least two of the second gate layers.

2. The semiconductor device as claimed in claim 1 , wherein the first difference is greater than the second difference.

3. The semiconductor device as claimed in claim 2 , further comprising:
first contacts extending in the vertical direction and being respectively in contact with the first gate layers; and
second contacts extending in the vertical direction and being respectively in contact with the second gate layers,
wherein an average of depths, by which the first contacts are respectively recessed into the first gate layers in the vertical direction, is greater than an average of depths, by which the second contacts are respectively recessed into the second gate layers in the vertical direction.

4. The semiconductor device as claimed in claim 2 , further comprising:
first contacts extending in the vertical direction and being respectively in contact with the first gate layers; and
second contacts extending in the vertical direction and being respectively in contact with the second gate layers,
wherein a maximum among depths, by which the first contacts are respectively recessed into the first gate layers in the vertical direction, is greater than a thickness of the central portion of each of the first gate layers.

5. The semiconductor device as claimed in claim 2 , wherein the thickness of the end portion of each of the at least two of the first gate layers is greater in the vertical direction than the thickness of the central portion of each of the at least two of the first gate layers.

6. The semiconductor device as claimed in claim 5 , wherein the thickness of the end portion of each of the at least two of the second gate layers is, in the vertical direction, equal to the thickness of the central portion of each of the at least two of the second gate layers.

7. The semiconductor device as claimed in claim 5 , wherein the thickness of the end portion of each of the at least two of the second gate layers is greater in the vertical direction than the thickness of the central portion of each of the at least two of the second gate layers.

8. The semiconductor device as claimed in claim 5 , wherein the thickness of the end portion of each of at least one of a lowest gate layer and an uppermost gate layer among the first gate layers is, in the vertical direction, equal to the thickness of the central portion of each of the at least one of the lowest gate layer and the uppermost gate layer among the first gate layers.

9. The semiconductor device as claimed in claim 1 , wherein the first difference is less than the second difference.

10. The semiconductor device as claimed in claim 1 , further comprising a channel structure passing through the first stack structure and the second stack structure in the vertical direction,
wherein the channel structure includes a first portion and a second portion, the first portion passing through the first stack structure, and the second portion passing through the second stack structure, and
wherein a diameter of a top of the first portion of the channel structure is greater than a diameter of a bottom of the second portion of the channel structure.

11. A semiconductor device, comprising:
a substrate;
stack structures stacked on the substrate in a vertical direction;
a channel structure passing through the stack structures in the vertical direction; and
contacts extending in the vertical direction and being in contact with the stack structures,
wherein the stack structures include at least one first-type stack structure and at least one second-type stack structure,
wherein the at least one first-type stack structure includes first gate layers and first interlayer insulating layers, the first gate layers being stacked alternately with the first interlayer insulating layers one by one in the vertical direction,
wherein the at least one second-type stack structure includes second gate layers and second interlayer insulating layers, the second gate layers being stacked alternately with the second interlayer insulating layers one by one in the vertical direction,
wherein each of the first gate layers includes a first shaped gate layer having a first shape and including a central portion and an end portion, the central portion of the first shaped gate layer being adjacent to the channel structure, the end portion of the first shaped gate layer being adjacent to one of the contacts that is in contact with the first shaped gate layer, and a thickness of the end portion of the first shaped gate layer being greater in the vertical direction than a thickness of the central portion of the first shaped gate layer, and
wherein each of the second gate layers includes a second shaped gate layer having a second shape and including a central portion and an end portion, the central portion of the second shaped gate layer being adjacent to the channel structure, the end portion of the second shaped gate layer being adjacent to one of the contacts that is in contact with the second shaped gate layer, and a thickness of the end portion of the second shaped gate layer being, in the vertical direction, equal to a thickness of the central portion of the second shaped gate layer.

12. The semiconductor device as claimed in claim 11 , wherein the thickness of the end portion of the second shaped gate layer is less in the vertical direction than the thickness of the end portion of the first shaped gate layer.

13. The semiconductor device as claimed in claim 11 , wherein an uppermost stack structure among the stack structures is one of the at least one second-type stack structure.

14. The semiconductor device as claimed in claim 11 , wherein an intermediate stack structure among the stack structures is one of the at least one first-type stack structure, the intermediate stack structure being between an uppermost stack structure among the stack structures and a lowest stack structure among the stack structures.

15. The semiconductor device as claimed in claim 11 , wherein at least one of a lowest gate layer and an uppermost gate layer among the first gate layers has the second shape.

16. An electronic system, comprising:

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jiyoung
• Kang Bumkyu
• Lim Joonsung
• Sung Sukkang

Classifications

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title