Memory device

Patent metadata

Field	Value
Publication number	US-10559583-B2
Application number	US-201715415248-A
Country	US
Kind code	B2
Filing date	Jan 25, 2017
Priority date	Jul 20, 2016
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a first direction, and a plurality of connecting electrodes connecting the unit electrodes to each other. The memory device also includes channel structures extending through the gate electrode layers in a direction perpendicular to the upper surface of the substrate, first common source lines extending in the first direction and interposed between the unit electrodes, and second common source lines extending in the first direction between the first common source lines and each having a first line and a second line separated from each other in the first direction by the connecting electrodes.

First claim

What is claimed is:

1. A memory device comprising:
a substrate having an upper surface and source regions at the upper surface;
a stack on the upper surface and including gate electrode layers, each of some of the gate electrode layers including unit electrodes and connecting electrodes, each of the unit electrodes extending longitudinally in a first direction, and each of the connecting electrodes disposed between a pair of the unit electrodes being closest to each other in a second direction and connecting the pair of the unit electrodes to each other;
first common source lines, each of the first common source lines connecting to a respective one of the source regions and extending longitudinally in the first direction to separate the stack into a plurality of blocks; and
second common source lines, each of the second common source lines connecting to a respective one of the source regions and extending longitudinally in the first direction, wherein
each of the second common source lines includes a first line and a second line separated in the first direction, by a respective one of the connecting electrodes, the first line and the second line in each of the second common source lines are disposed at the same position in the second direction,
the first lines included in a pair of the second common source lines being closest to each other in the second direction, in at least one of the plurality of blocks, have different lengths in the first direction,
in at least one of the plurality of blocks, two of the second lines have the same length in the first direction, and one of the second lines between the two of the second lines have a different length from the two of the second lines in the first direction, and
a distance between the first line and the second line included in one of the pair of the second common source lines is substantially the same with a distance between the first line and the second line included in another one of the pair of the second common source lines.

2. The memory device of claim 1 , wherein in a region between the first common source lines that are closest to each to other in the second direction, one of the connecting electrodes is offset from another one of the connecting electrodes in the first direction.

3. The memory device of claim 2 , wherein two of the connecting electrodes that are closest to each other in the second direction in said region are disposed in different positions in both of the first direction and the second direction.

4. The memory device of claim 1 , wherein the first line and the second line included in each of the second common source lines are conductive.

5. The memory device of claim 1 , wherein the second lines included in the pair of the second common source lines being closest to each other in the second direction have different lengths in the first direction.

6. The memory device of claim 1 , wherein an area between the second lines being adjacent in the second direction includes cell contacts, and
as compared to the area between the second lines being adjacent in the second direction, an area between the first lines being adjacent in the second direction further includes channel structures penetrating the stack and connecting to the upper surface of the substrate.

7. The memory device of claim 1 , further comprising:
channel structures connected to bit lines above the stack and penetrating the stack; and
dummy channel structures separated from the bit lines.

8. The memory device of claim 7 , wherein the dummy channel structures are disposed adjacent to edges of at least a portion of the gate electrode layers.

9. The memory device of claim 7 , wherein the channel structures between the first lines of the second common source lines is disposed farther away from the second lines of the second common source lines, than dummy channel structures between the first lines of the second common source lines.

10. he memory device of claim 1 , wherein the number of the unit electrodes closest to one side of the second line included one of the second common source lines is different from the number of the unit electrodes closest to another side of said second line included said one of the second common source lines.

11. The memory device of claim 1 , wherein at least a portion of the unit electrodes has a stepped structure in the first direction and the second direction, in an area where said at least a portion of the unit electrodes are connected to cell contacts.

12. A memory device, comprising
a substrate having an upper surface;
gate electrode layers on the upper surface;
channel structures penetrating the gate electrode layers and connected to the upper surface;
first common source lines, each of the first common source lines extending longitudinally in a first direction;
second common source lines, each of the second common source lines extending longitudinally in the first direction and including a first line and a second line; and
cell contacts connected to the gate electrode layers, wherein
at least a portion of the cell contacts disposed at the same position in the first direction have different lengths to each other in a third direction perpendicular to the upper surface, and
the second lines of the second common source lines are disposed between said at least a portion of the cell contacts.

13. The memory device of claim 12 , wherein the channel structures are disposed only between the first lines of the second common source lines and between one of the first lines of the second common source lines and the first common source line.

14. The memory device of claim 12 , wherein, in an area adjacent to the second lines of the second common source lines, a difference of lengths between the cell contacts closest in the first direction is greater than a difference of lengths between the cell contacts closest in the second direction.

15. A memory device comprising:
a substrate having an upper surface;
gate electrode layers on the upper surface, each of the gate electrode layers including unit electrodes extending longitudinally in a first direction and connecting electrodes disposed between a pair of the unit electrodes being closest to each other in a second direction, and the pair of the unit electrodes disposed in a same height from the upper surface;
first common source lines, each of the first common source lines extending longitudinally in the first direction;
second common source lines, each of the second common source lines extending longitudinally in the first direction and including a first line and a second line; and
wherein both of the first line and the second line are conductive,
in a region between respective ones of the first common source lines that are closest to each other in the second direction, two or more of the second common source lines are disposed, and one among two or more of second common source lines is closest to another one among the two or more of the second common source lines in the second direction,
in the region, a length of the first line included in the one among the two or more of the second common source lines is greater than a length of the first line included in the another one among the two or more of the second common source lines, and a length of the second line included in the one among the two or more of the second common source lines is less than a length of the second line included in the another one among the two or more of the second common source lines.

16. The memory device of claim 15 , further comprising:
cell contacts connected to the gate electrode layers, wherei

Assignees

• Park Su Jin
• Kim Sun Young
• Yun Jang Gn
• Samsung Electronics Co Ltd

Inventors

• Park Su Jin
• Kim Sun Young
• Yun Jang Gn

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic