Vertical semiconductor device

Patent metadata

Field	Value
Publication number	US-10658374-B2
Application number	US-201916416319-A
Country	US
Kind code	B2
Filing date	May 20, 2019
Priority date	Dec 14, 2016
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

First claim

What is claimed is:

1. A method of manufacturing a vertical semiconductor device, the method comprising:
forming a plurality of conductive layer patterns spaced apart from each other by a plurality of interlayer insulating layer patterns in a vertical direction on a substrate,
wherein, a first conductive layer pattern of the conductive layer patterns extends from one sidewall of adjacent interlayer insulating layer patterns and comprises a pad region, wherein the pad region includes a raised pad portion protruding from a surface of the first conductive layer pattern and one end of the raised pad portion is rounded; and
forming a contact plug to be in contact with the raised pad portion of the first conductive layer pattern.

2. The method of claim 1 , wherein another end of the raised pad portion is formed apart from the one end of the raised pad portion in a horizontal direction in which the first conductive layer pattern extends, wherein the other end of the raised pad portion is also rounded.

3. The method of claim 1 , wherein some of the interlayer insulating layer patterns comprise a recess portion recessed from one end of each of two adjacent conductive layer patterns.

4. The method of claim 1 , wherein a thickness of an uppermost conductive layer pattern of the conductive layer patterns is thicker than that of the first conductive layer pattern having the raised pad portion under the uppermost conductive layer pattern.

5. The method of claim 1 , wherein the conductive layer patterns have an inclined portion, and a lower conductive layer pattern of the conductive layer patterns comprises the first conductive layer pattern.

6. The method of claim 1 , wherein the pad region is formed at an edge of the first conductive layer pattern, and one lower end of the first conductive layer pattern under the pad region is rounded.

7. A method of manufacturing a vertical semiconductor device, the method comprising:
forming a plurality of interlayer insulating layer patterns and a plurality of sacrificial layer patterns stacked alternately in a stepped form in a vertical direction on a substrate;
forming an additional sacrificial layer on surfaces and sidewalls of the sacrificial layer patterns exposed by adjacent interlayer insulating layer patterns, wherein one end of the additional sacrificial layer is rounded on each of the sacrificial layer patterns;
forming an upper interlayer insulating layer on the interlayer insulating layer patterns, the sacrificial layer patterns, and the additional sacrificial layer;
removing the sacrificial layer patterns and the additional sacrificial layer to form grooves;
filling the grooves with a plurality of conductive layer patterns,
wherein the conductive layer patterns comprise pad regions each extending from one sidewall of an interlayer insulating layer pattern and the pad regions comprise raised pad portions protruding from surfaces of the conductive layer patterns, and one end of each of the raised pad portions is rounded; and
forming a plurality of contact plugs configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portions of the conductive layer patterns.

8. The method of claim 7 , wherein the additional sacrificial layer is rounded at another end located opposite to the one end on the sacrificial layer patterns.

9. The method of claim 8 , wherein the additional sacrificial layer is formed to extend horizontally on one sidewall of each of the adjacent interlayer insulating layer patterns, and
the one end and the other end of the additional sacrificial layer are formed horizontally close to or distant from the one sidewall of the adjacent interlayer insulating layer patterns, respectively.

10. The method of claim 7 , wherein the forming of the additional sacrificial layer comprises:
forming an additional insulating layer rounded at one end on the sacrificial layer patterns exposed by the interlayer insulating layer patterns; and
implanting impurities into the additional insulating layer to form the additional sacrificial layer having an etch rate that is higher than an etch rate of the additional insulating layer.

11. The method of claim 10 , wherein the forming of the additional insulating layer comprises oxidizing surfaces and side surfaces of the sacrificial layer patterns exposed by the interlayer insulating layer patterns.

12. The method of claim 7 , further comprising, after the forming of the interlayer insulating layer patterns and the sacrificial layer patterns, forming a recess portion in which one end of each of the interlayer insulating layer patterns is recessed inwardly from one sidewall of each adjacent sacrificial layer pattern.

13. The method of claim 12 , wherein the recess portion is formed by isotropically etching one end of each interlayer insulating layer pattern below a respective adjacent sacrificial layer pattern.

14. The method of claim 7 , wherein another end of each raised pad portion is formed apart from the one end of the raised pad portion in a horizontal direction in which the first conductive layer patterns extend, and the other end of each raised pad portion is also rounded.

15. The method of claim 14 , wherein one lower end of each conductive layer pattern close to the one end of the raised pad portion is rounded.

16. A method of manufacturing a vertical semiconductor device, the method comprising:
forming a plurality of interlayer insulating layer patterns and a plurality of sacrificial layer patterns stacked alternately in a vertical direction on a substrate;
photolithographically etching some of the interlayer insulating layer patterns and the sacrificial layer patterns and exposing surfaces and sidewalls of a portion of the interlayer insulating layer patterns and the sacrificial layer patterns and a surface of a lower sacrificial layer pattern of the sacrificial layer patterns;
forming an additional sacrificial layer on the surfaces and sidewalls of the sacrificial layer patterns exposed and the surface of the lower sacrificial layer pattern, wherein the additional sacrificial layer is rounded at one end on the lower sacrificial layer pattern;
forming an upper interlayer insulating layer on the interlayer insulating layer patterns, the sacrificial layer patterns, the lower sacrificial layer pattern, and the additional sacrificial layer;
removing the sacrificial layer patterns, the lower sacrificial layer pattern, and the additional sacrificial layer to form grooves on the substrate;
filling the grooves with a plurality of conductive layer patterns,
wherein a conductive layer pattern of the conductive layer patterns filled in a groove by removing the lower sacrificial layer pattern comprises a pad region extending from one sidewall of each adjacent interlayer insulating layer pattern, wherein the pad region comprises a raised pad portion protruding from a surface of the conductive layer pattern, and the raised pad portion is rounded at one end; and
forming a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the conductive layer pattern.

17. The method of claim 16 , wherein some of the interlayer insulating layer patterns and the sacrificial layer patterns are photolithographically etched to form interlayer insulating layer patterns and sacrificial layer patterns having an inclined portion on the substrate.

18. The method of claim 16 , wherein the forming of the additional sacrificial layer comprises:
forming an additional insulating layer on the sacri

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jo-Young
• Kang Chang-Seok
• Lee Chang-Sup
• Jang Se-Mee

Classifications

• H01L27/11524

  Electricity · mapped topic

• H01L21/76877

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11575 Primary

  Electricity · mapped topic

• H01L27/11548

  Electricity · mapped topic