Within-array through-memory-level via structures and method of making thereof

Patent metadata

Field	Value
Publication number	US-10249640-B2
Application number	US-201615176674-A
Country	US
Kind code	B2
Filing date	Jun 8, 2016
Priority date	Jun 8, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a memory-level assembly located over a substrate and including an alternating stack of insulating layers and composite layers, wherein the insulating layers and the composite layers alternate along a vertical direction that is perpendicular to a top surface of the substrate, wherein each of the composite layers comprises:
a respective electrically conductive layer; and
a respective spacer dielectric portion, wherein the respective electrically conductive layer and spacer dielectric portion are laterally adjoined to each other, and wherein each vertically neighboring pair of the spacer dielectric portions is vertically spaced apart from each other by a thickness of an intervening one of the insulating layers;

memory stack structures vertically extending through the alternating stack and each of the memory stack structures comprising:
a respective memory film; and
a respective vertical semiconductor layer that is laterally surrounded by the respective memory film; and

at least one through-memory-level via structure that vertically extends through each of the spacer dielectric portions and the insulating layers, wherein the at least one through-memory-level via structure extends below bottommost surfaces of the memory stack structures.

2. The semiconductor structure of claim 1 , wherein:
each of the memory stack structures passes through the electrically conductive layers, and does not pass through any of the spacer dielectric portions; and
the at least one through-memory-level via structure vertically extends at least from a first horizontal plane including a topmost surface of the memory-level assembly to a second horizontal plane including a bottommost surface of the memory-level assembly.

3. The semiconductor structure of claim 1 , wherein the at least one through-memory-level via structure extends through, and is laterally surrounded by, each of the spacer dielectric portions within the alternating stack.

4. The semiconductor structure of claim 3 , wherein:
each of the spacer dielectric portions directly contacts each of the at least one through-memory-level via structure; and
each of the at least one through-memory level via structure is laterally spaced from the electrically conductive layers by the spacer dielectric portions,
wherein the at least one through-memory level via structure consists of at least one conductive material and is free of any dielectric material therein.

5. The semiconductor structure of claim 1 , wherein the memory stack structures are laterally spaced from the at least one through-memory-level via structure by a support pillar region that laterally surrounds the spacer dielectric portions and including a plurality of support pillar structures.

6. The semiconductor structure of claim 5 , wherein:
each of the support pillar structures and each of the memory stack structures comprise a set of the same material layers including a respective memory film and a respective vertical semiconductor layer;
at least one topmost electrically conductive layer comprises a drain select gate electrode;
at least one bottommost electrically conductive layer comprises a source select gate electrode; and
the electrically conductive layers located between the at least one top most electrically conductive layer and the at least one bottommost electrically conductive layer comprise control gate electrodes for a three-dimensional NAND memory device.

7. The semiconductor structure of claim 5 , wherein the plurality of support pillar structures comprises a first subset of support pillar structures that directly contact the electrically conductive layers and the spacer dielectric portions.

8. The semiconductor structure of claim 7 , wherein the plurality of support pillar structures comprises a second subset of support pillar structures that directly contact the electrically conductive layers and does not directly contact, and is laterally spaced from, the spacer dielectric portions.

9. The semiconductor structure of claim 8 , wherein the plurality of support pillar structures comprises a third subset of support pillar structures that directly contact the spacer dielectric portions and does not directly contact, and is laterally spaced from, the electrically conductive layers.

10. The semiconductor structure of claim 1 , further comprising a plurality of laterally-elongated contact via structures that vertically extend through the memory-level assembly and laterally extend along a first horizontal direction, wherein the spacer dielectric portions are located between a pair of laterally-elongated contact via structures that are spaced apart along the first horizontal direction.

11. The semiconductor structure of claim 1 , wherein:
each of the spacer dielectric portions within the alternating stack has a respective pair of concave sidewalls and a respective pair of substantially parallel straight sidewalls;
each pair of concave sidewalls faces a first horizontal direction and are laterally spaced apart along the first horizontal direction; and
each pair of substantially parallel straight sidewalls is parallel to the first horizontal direction.

12. The semiconductor structure of claim 11 , further comprising a pair of contact trenches including a pair of laterally-elongated contact via structures, wherein the pair of contact trenches vertically extend through the memory-level assembly, laterally extend along the first horizontal direction, laterally spaced apart along the first horizontal direction, and are substantially co-linear with each other along the first horizontal direction, wherein the spacer dielectric portions-are located between the pair of contact trenches.

13. The semiconductor structure of claim 11 , wherein a plurality of spacer dielectric portions among the spacer dielectric portions of the alternating stack is laterally surrounded by, and is located within a hole through, a respective one of the electrically conductive layers within the alternating stack.

14. The semiconductor structure of claim 12 , wherein:
each pair of concave sidewalls are substantially equidistant from a most proximal sidewall of the pair of contact trenches.

15. The semiconductor structure of claim 1 , wherein:
semiconductor devices of a driver circuit for the memory level assembly is located below a horizontal plane including a bottom most surface of the memory level assembly;
a lower level metal interconnect structure electrically contacts, and overlies, at least one node of the semiconductor devices and underlies the memory level assembly; and
the at least one through-memory-level via structure contacts a top surface of the lower level metal interconnect structure and a bottom surface of an upper level metal interconnect structure overlying a horizontal plane including a topmost surface of the memory-level assembly.

16. The semiconductor structure of claim 1 , wherein:
two or more topmost layers among the electrically conductive layers comprise drain select gate electrodes;
each of the drain select gate electrodes is physically divided into multiple portions by a dielectric material portion around the at least one through-memory-level via structure; and
a stepped region is provided in which a first drain select electrode extends closer to the at least one through-memory-level via structure than a second drain select electrode located above the first drain select electrode is to the at least one through-memory-level via structure.

17. The semiconductor structure of claim 1 , wherein:
the memor

Assignees

• Sandisk Technologies Llc

Inventors

• Yu Jixin
• Lu Zhenyu
• Chu Alexander
• Yamaguchi Kensuke
• Ogawa Hiroyuki
• Mao Daxin
• Li Yan
• Alsmeier Johann

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic