Semiconductor device including stack structures having R-type pad and P-type pad of different thickness

Patent metadata

Field	Value
Publication number	US-10535679-B2
Application number	US-201816136474-A
Country	US
Kind code	B2
Filing date	Sep 20, 2018
Priority date	Mar 28, 2018
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

First claim

What is claimed is:

1. A semiconductor device comprising:
lower gate electrodes placed on a substrate and spaced apart from one another in a vertical direction;
upper gate electrodes placed over the lower gate electrodes and spaced apart from one another in the vertical direction;
an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than that of the lower gate electrode or upper gate electrode connected to the R-type pad; and
a P-type pad extending from one end of at least one electrode among the lower gate electrodes to which the R-type pad is not connected and having a different thickness than the R-type pad,
wherein the P-type pad comprises a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

2. The semiconductor device of claim 1 , further comprising:
a lower channel hole passing through the lower gate electrodes; and
an upper channel hole communicating with the lower channel hole and passing through the upper gate electrodes,
wherein the first pad has an upper surface corresponding to a level of an upper end of the lower channel hole.

3. The semiconductor device of claim 1 , further comprising:
a lower channel structure passing through the lower gate electrodes; and
an upper channel structure electrically connected to the lower channel structure and passing through the upper gate electrodes,
wherein the first pad has an upper surface corresponding to a level of an upper end of the lower channel structure.

4. The semiconductor device of claim 1 , wherein the P-type pad further comprises a second pad extending from an uppermost upper gate electrode among the upper gate electrodes.

5. The semiconductor device of claim 1 , further comprising:
an interlayer insulating layer configured to cover upper surfaces and side surfaces of the R-type pad and the P-type pad,
wherein the interlayer insulating layer comprises a first interlayer insulating layer adjacent to the substrate and a second interlayer insulating layer provided over the first interlayer insulating layer, and
wherein the first pad has an upper surface corresponding to a level of an interface between the first interlayer insulating layer and the second interlayer insulating layer.

6. The semiconductor device of claim 1 , wherein the P-type pad comprises a third pad extending from a lowermost lower gate electrode among the lower gate electrodes.

7. The semiconductor device of claim 6 , further comprising:
insulating layers stacked alternately with the lower gate electrodes and the upper gate electrodes;
a lower channel hole passing through the lower gate electrodes and lower insulating layers of the insulating layers; and
an upper channel hole communicating with the lower channel hole and passing through the upper gate electrodes and upper insulating layer of the insulating layers,
wherein the insulating layers comprise a first insulating layer being in contact with an upper surface of the third pad and having a greater thickness than the other insulating layers.

8. The semiconductor device of claim 7 , wherein the first insulating layer covers the upper surface of the third pad.

9. The semiconductor device of claim 7 ,
wherein the insulating layers comprises a second insulating layer having an upper surface corresponding to a level of an upper end of the lower channel hole, and
wherein the first pad has an upper surface corresponding to a level of a lower surface of the second insulating layer.

10. The semiconductor device of claim 1 , further comprising:
an R-type contact being in contact with the R-type pad; and
a P-type contact being in contact with the P-type pad.

11. The semiconductor device of claim 10 , further comprising a coupling wire that is commonly connected to the R-type contact and the P-type contact.

12. The semiconductor device of claim 10 , wherein the P-type contact passes through the P-type pad.

13. The semiconductor device of claim 12 , wherein the P-type contact is in contact with a lower gate electrode or upper gate electrode provided under the P-type pad.

14. The semiconductor device of claim 1 ,
wherein the P-type pad has an upper surface coplanar with an upper surface of the at least one electrode from which the P-type pad extends and a lower surface coplanar with a lower surface of the at least one electrode from which the P-type pad extends.

15. The semiconductor device of claim 1 , wherein the P-type pad has a thickness corresponding to that of the at least one electrode from which the P-type pad extends.

16. The semiconductor device of claim 1 , further comprising:
insulating layers stacked alternately with the lower gate electrodes and the upper gate electrodes,
wherein an upper surface of the R-type pad has a higher level than a lower surface of an insulating layer placed over the R-type pad.

17. A semiconductor device comprising:
a lower stack structure comprising lower gate electrodes and lower insulating layers alternately stacked on a substrate;
an upper stack structure comprising upper gate electrodes and upper insulating layers alternately stacked on the lower stack structure;
at least one dummy word line spaced apart from the lower gate electrodes and the upper gate electrodes in a vertical direction;
a channel structure passing though the lower stack structure, the upper stack structure, and the dummy word line in the vertical direction;
an R-type pad extending from one end of each of the lower gate electrodes and the upper gate electrodes in a horizontal direction and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad;
a P-type pad extending from one end of the dummy word line in the horizontal direction and having the same thickness as the dummy word line connected to the P-type pad;
an R-type contact connected to the R-type pad in the vertical direction;
a P-type contact connected to the P-type pad in the vertical direction; and
a coupling wire commonly connected to the R-type contact and the P-type contact.

18. The semiconductor device of claim 17 ,
wherein the dummy word line comprises a first dummy word line placed between the lower stack structure and the upper stack structure, and
wherein the P-type pad comprises a first pad extending from one end of the first dummy word line.

19. The semiconductor device of claim 17 ,
wherein the dummy word line comprises a second dummy word line placed on top of the upper stack structure, and
wherein the P-type pad comprises a second pad extending from one end of the second dummy word line.

20. A semiconductor device comprising:
gate electrodes placed on a substrate and spaced apart from one another in a first direction perpendicular to a second direction;
insulating layers stacked alternately with the gate electrodes;
an R-type pad extending in the second direction from one end of at least one gate electrode among the gate electrodes and having a greater thickness than the gate electrode connected to the R-type pad;
a P-type pad extending in the second direction from one end of at least one gate electrode to which the R-type pad is not connected among the gate electrodes and having a different thickness than the R-type pad;
a lower interlayer insulating layer covering a first portion of an upper surface of the R-type pad and contacting an upper surface of the substrate;
an upper interlayer insulating layer cove

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Seok Cheon
• Kim Boh Chang
• Min Chung Ki
• Park Ji Hoon
• You Byung Kwan

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title