Method of reprogramming data in nonvolatile memory device, method of programming data in nonvolatile memory device, nonvolatile memory device performing the same, and method of operating nonvolatile memory device using the same

Patent metadata

Field	Value
Publication number	US-12154646-B2
Application number	US-202217816601-A
Country	US
Kind code	B2
Filing date	Aug 1, 2022
Priority date	Dec 23, 2021
Publication date	Nov 26, 2024
Grant date	Nov 26, 2024

Abstract

In a method of reprogramming data in a nonvolatile memory device including a plurality of pages each of which includes a plurality of memory cells, first page data programmed in a first page is read from among a plurality of page data programmed in the plurality of pages. The plurality of page data have a threshold voltage distribution including a plurality of states. An error correction code (ECC) decoding is performed on the first page data. A reprogram operation is selectively performed on target bits in which an error occurs among a plurality of bits included in the first page data based on a result of performing the ECC decoding on the first page data and a reprogram voltage. The target bits correspond to a first state among the plurality of states. A voltage level of the reprogram voltage is adaptively changed.

First claim

What is claimed is:

1. A method of reprogramming data in a nonvolatile memory device including a plurality of pages each of which includes a plurality of memory cells, the method comprising:
reading first page data programmed in a first page from among a plurality of page data programmed in the plurality of pages, the plurality of page data having a threshold voltage distribution including a plurality of states;
performing an error correction code (ECC) decoding on the first page data;
determining a number of times program loops were performed to program the first page data based on first program loop completion information associated with the first page;
determining a reprogram voltage based on the number of times;
selectively performing a reprogram operation on target bits in which an error occurs among a plurality of bits included in the first page data based on a result of performing the ECC decoding on the first page data and the reprogram voltage, the target bits corresponding to a first state among the plurality of states.

2. The method of claim 1 , wherein: the first page in which the first page data is programmed includes a first data region in which the first page data is stored and a first spare region, a second page in which second page data is programmed after the first page data is programmed includes a second data region in which the second page data is stored and a second spare region, and the first program loop completion information representing the number of times the program loops were performed to program the first page data is stored in the second spare region.

3. The method of claim 2 , wherein the voltage level of the reprogram voltage for performing the reprogram operation on the target bits is determined based on the first program loop completion information.

4. The method of claim 3 , wherein the voltage level of the reprogram voltage increases as the number of times the program loops are performed while the first page data is programmed increases.

5. The method of claim 3 , wherein the voltage level of the reprogram voltage is lower than a loop completion voltage level of a program voltage used while the first page data is programmed.

6. The method of claim 2 , wherein only a part of a first number corresponding to the first program loop completion information is stored in the second spare region.

7. The method of claim 2 , wherein: third page data is programmed before the first page data is programmed, second program loop completion information representing a number of times program loops are performed while the third page data is programmed is stored in the first spare region, and the voltage level of the reprogram voltage for performing the reprogram operation on the target bits is determined based on the second program loop completion information.

8. The method of claim 1 , wherein the voltage level of the reprogram voltage is determined based on a shifted amount of threshold voltages due to a change in the threshold voltage distribution.

9. The method of claim 1 , wherein performing the ECC decoding on the first page data comprises:
reading first parity data corresponding to the first page data;
performing the ECC decoding based on the first page data and the first parity data to generate first error corrected page data and to check a first error number of the first page data, the first error number representing a number of errors in the first page data; and
determining whether the reprogram operation is performed on the target bits based on the first error number and a reference number.

10. The method of claim 9 , wherein determining whether the reprogram operation is performed on the target bits comprises:
determining that the reprogram operation is performed on the target bits when the first error number is greater than the reference number; and
determining that the reprogram operation is not performed on the target bits when the first error number is less than or equal to the reference number.

11. The method of claim 10 , wherein selectively performing the reprogram operation on the target bits comprises:
selecting first bits in which an error occurs from among the plurality of bits by comparing the first page data before the ECC decoding is performed with the first error corrected page data after the ECC decoding is performed, when the first error number is greater than the reference number;
selecting second bits corresponding to the first state from among the plurality of bits by performing a read operation on two or more pages including the first page among the plurality of pages;
selecting the target bits based on the first bits and the second bits; and
reprogramming only target memory cells in which the target bits are stored by applying the reprogram voltage only to the target memory cells.

12. The method of claim 11 , wherein the target bits are a part of the first bits and a part of the second bits.

13. The method of claim 11 , wherein the reprogram voltage is applied one time to the target memory cells.

14. The method of claim 1 , wherein the first state is a highest state among the plurality of states.

15. The method of claim 1 , further comprising: performing at least one data recovery operation on the first page.

16. The method of claim 1 , further comprising:
performing a reclaim operation in which data programmed in a first memory block including the first page is copied and programmed to a second memory block.

17. A method of programming data in a nonvolatile memory device including a plurality of pages each of which includes a plurality of memory cells, the method comprising:
programming first page data to a first page among the plurality of pages by performing a program loop including a program operation and a program verification operation at least one time, the program operation being performed based on a program voltage, the program verification operation being performed based on a program verification voltage; and
storing first program loop completion information representing a number of times program loops are performed while the first page data is programmed in a second page different from the first page.

18. The method of claim 17 , wherein: the first page includes a first data region and a first spare region, the second page includes a second data region and a second spare region, the first page data is stored in the first data region, and the first program loop completion information is stored in the second spare region.

19. A method of operating a nonvolatile memory device including a plurality of pages each of which includes a plurality of memory cells, the method comprising:
programming a plurality of page data to the plurality of pages, the plurality of page data having a threshold voltage distribution including a plurality of states; and
selectively reprogramming the plurality of page data,
wherein programming the plurality of page data comprises:
programming first page data to a first page among the plurality of pages by performing a program loop including a program operation and a program verification operation at least one time, the program operation being performed based on a program voltage, the program verification operation being performed based on a program verification voltage; and
storing first program loop completion information representing a number of times program loops are performed while the first page data is programmed in a second page different from the first page, wherein selectively reprogramming the plurality of page data compris

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seok Junyeong
• SONG Younggul
• Oh Eunchu

Classifications

• G11C2029/5004

  Voltage · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title