Memory refresh methods and apparatuses

Patent metadata

Field	Value
Publication number	US-10109357-B2
Application number	US-201514867985-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Aug 31, 2011
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

First claim

The invention claimed is:

1. A method of operating a memory device, comprising:
operating a memory controller coupled to multiple blocks of memory cells, each block including multiple pages of memory cells, the controller operated to read stored electrical states in portions of the memory, the memory controller further performing the following operations,
tracking the number of reads of a first group of pages of memory cells with a counter;
determining that the number of memory page reads of the first group of pages exceeds a page read threshold;

in response to determining that a number of memory page reads exceeds the page read threshold, marking a block of the non-volatile memory containing the first group of pages for refresh;
determining the number of memory page reads of a second group of pages of the non-volatile memory, and determining that the number of memory page reads does not exceed a page read threshold;
subsequent to determining that the number of memory page reads of the second group of pages does not exceed the page read threshold, reading data stored in electrical states from some portion of the second group of pages and checking one or more portions of the second group of pages for errors;
determining that the number of errors in the second group of pages exceeds an error threshold;
marking the second group of pages for refresh; and

performing refresh operations of the stored electrical states of memory cells in each of the first and second groups of pages.

2. The method of claim 1 , wherein determining whether the number of memory page reads of a memory block in response to a read request exceeds the page read threshold comprises:
incrementing an up-counter responsive to reading a page of memory; and
determining whether a value of the incremented up-counter exceeds a particular value.

3. The method of claim 1 , wherein determining whether the number of memory page reads exceeds the page read threshold comprises:
decrementing a down-counter responsive to reading a page of memory; and
determining whether a value of the decremented down-counter is below a particular value.

4. The method of claim 1 , wherein reading data stored in some portion of the second group of pages comprises reading data stored in memory pages of one or more identified blocks of memory.

5. The method of claim 4 , wherein reading data stored in some portion of the second group of pages comprises reading data stored in memory pages of a single identified block of memory.

6. The method of claim 4 , wherein reading data stored in some portions of the second group of pages comprises reading data stored in a memory pages of a block of memory identified by a refresh block pointer.

7. The method of claim 1 , wherein marking the block of memory for refresh comprises marking the block of memory for refresh if a number of errors in any page of the read data exceeds a threshold.

8. An apparatus, comprising:
a plurality of pages of non-volatile memory, the non-volatile memory storing data in the form of stored electrical states in memory cells; and
a memory controller coupled to the plurality of pages of non-volatile memory, the controller configured to,
perform a first determination of the number of memory page reads of at least some first portion of the pages of non-volatile memory, and determining that a number of memory page reads exceeds a first page read threshold,
in response to determining that a number of memory page reads of the first portion of pages exceeds the first page read threshold, marking some portion number of the first portion of pages of non-volatile memory for refresh;
subsequently performing a second determination of the number of memory page reads of at least some second portion of the pages of non-volatile memory, and determining that the number of memory page reads of the second portion of pages does not exceed a second page read threshold;
in response to determining that the number of memory page reads of the second portion does not exceed the page read threshold, reading data from some portion of the pages of memory of the second portion to check the pages of memory for errors,
determining that the number of errors in the second portion of the pages of memory exceeds an error threshold; and
marking the second portion of the pages of memory for background refresh; and refreshing data in each of the first portion of the pages and the second portion of the pages in response to the respective first and second determinations.

9. The apparatus of claim 8 , wherein the plurality of pages of non-volatile memory are disposed in a flash memory card.

10. The apparatus of claim 8 , wherein the controller is further configured to store in memory the current block and page being read as part of the refresh.

11. The apparatus of claim 8 , wherein the controller is further configured to store an address of the block of memory marked for background refresh in nonvolatile memory.

12. The apparatus of claim 11 , wherein the controller is further configured to store an address of a page location pointing to the block of memory marked for background refresh in volatile memory.

13. The apparatus of claim 12 , wherein the controller is further configured to restart a background refresh method in response to a power cycle, wherein the controller is configured to begin the refresh at the address stored in nonvolatile memory.

14. A memory controller coupled to multiple blocks of non-volatile memory cells, each block including multiple pages of non-volatile memory cells, and configured to perform operations comprising:
reading data in the form of stored electrical states in portions of the blocks of memory cells,
determining whether reads of a first group of pages of the memory cells exceeds a page read threshold;
in response to determining that reads of the first group of pages does not exceed the page read threshold, checking portions of the read data for errors, and determining that the read data includes a number of errors that exceeds an error threshold; and
marking the one or more blocks of memory containing the first group of pages of memory for background refresh; and
refreshing the one or more blocks containing the first group of pages of non-volatile memory cells.

15. The controller of claim 14 , wherein multiple blocks of memory cells to which the controller is coupled comprises multi-level nonvolatile memory cells.

16. The controller of claim 14 , wherein the controller is further configured to use error correction code data associated with data read from the first group of pages of memory to determine whether errors are present in the read data.

17. The controller of claim 14 , wherein the controller is further configured to store a refresh block pointer identifying a block of memory not yet checked for errors.

18. The controller of claim 14 , wherein the controller is further configured to refresh at a rate of refresh that avoids uncorrectable read disturb errors in the blocks of memory before refresh of each block occurs.

19. The apparatus of claim 8 , further comprising:
determining that the number of errors in in a second group of pages of memory cells contains a number of errors exceeding the error threshold; and
in response to such determination, at least the second group of pages of non-volatile memory cells for refresh.

20. A method of operating a memory array, comprising:
through use of a memory controller associated with the memory array, the memory array including multiple memory

Assignees

• Micron Technology Inc

Inventors

• Blodgett Greg A

Classifications

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/1417

  Boot up procedures · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G06F11/0727 Primary

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title