Memory refresh methods and apparatuses

Patent metadata

Field	Value
Publication number	US-10290359-B2
Application number	US-201715684763-A
Country	US
Kind code	B2
Filing date	Aug 23, 2017
Priority date	Aug 31, 2011
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

First claim

The invention claimed is:

1. A method, comprising:
checking a respective portion of non-volatile memory of a non-volatile memory device for errors in response to the memory device being power cycled, wherein a different portion of the memory is checked for errors in response to each of multiple power cycles;
checking additional portions of the memory for errors during operation of the memory after a predetermined number of pages of the memory have been read over multiple power cycles;
determining that a number of errors in a first checked additional portion exceeds a threshold; and
reprogramming corrected data for the first checked additional portion to the memory.

2. The method of claim 1 , wherein the respective portion of non-volatile memory of a non-volatile memory device checked for errors in response to the memory device being power cycled is a group of pages of the memory, wherein the group of pages are in a first block of memory.

3. The method of claim 2 , further comprising:
determining that errors exceeding a threshold exist in the group of pages in the first block; and
marking the first block of memory for refresh.

4. The method of claim 3 , further comprising reprogramming the marked first block of memory to another block location in physical memory.

5. The method of claim 1 , further comprising in response to the memory device being power cycled determining that a portion of the memory is already marked for refresh.

6. The method of claim 5 , further comprising refreshing the respective portion of the memory already marked for refresh.

7. The method of claim 1 , further comprising maintaining a refresh block pointer identifying a next respective memory block to be checked for errors in response to a power cycle.

8. A device including memory, comprising:
a memory array comprising non-volatile memory cells; and
a memory controller operable to,
check a respective portion of non-volatile memory of a non-volatile memory device for errors in response to the memory device being power cycled, wherein a different portion of the memory is checked for errors in response to each of multiple power cycles;
check additional portions of the memory for errors during operation of the memory after a predetermined number of pages of the memory have been read over multiple power cycles;
determine that a number of errors in a first checked additional portion exceeds a threshold; and
reprogram corrected data to the memory for that s checked additional portion.

9. The memory device of claim 8 , wherein the respective portion of non-volatile memory of a non-volatile memory device checked for errors in response to the memory device being power cycled is a group of pages of the memory, wherein the group of pages are in a first block of memory.

10. The memory device of claim 9 , wherein the controller is further operable to determine that errors exceeding a threshold exist in the group of pages in the first block of memory; and
in response to such determination, mark the first block of memory for refresh.

11. The memory device of claim 9 , wherein the controller is further operable to reprogram the marked first block of memory to another block location in physical memory.

12. The apparatus of claim 8 , wherein the array of nonvolatile memory comprises an array of NAND flash memory cells.

13. The apparatus of claim 8 , wherein the controller being operable to check a portion of the non-volatile memory for errors comprises the controller being operable to:
read data from the portion of the non-volatile memory;
use error correction code data associated with the read data to determine a number of errors present in the read data; and
determine if the number of errors exceeds a threshold.

14. The apparatus of claim 8 , wherein the memory controller is further operable to store a refresh block pointer identifying a portion of the memory to next be checked for errors in response to power cycling of the memory device.

15. A method of operating a memory array, when the memory array comprises multiple blocks of non-volatile memory cells, each block including multiple pages of non-volatile memory cells, the method comprising:
determining the number of memory page reads of a first group of pages of the non-volatile memory cells, and determining that a number of memory page reads exceeds a page read threshold,
in response to determining that a number of memory page reads exceeds the page read threshold, marking a first block of the non-volatile memory containing the first group of pages for refresh;
determining the number of memory page reads of a second group of pages of the non-volatile memory, and determining that the number of memory page reads does not exceed a page read threshold;
subsequent to determining that the number of memory page reads of the second group of pages does not exceed the page read threshold, reading data from some portion of the second group of pages and checking the pages for errors;
determining that the number of errors in the portion of the second group of pages exceeds an error threshold;
marking a second block containing the second group of pages for refresh; and
refreshing data stored in each of the first and second blocks.

16. The method of claim 15 , wherein determining the number of page reads of a first group of pages is performed in response to a power cycle of the memory device; and wherein determining the number of page reads of a second group of pages is performed in response to a different power cycle of the memory device.

17. The method of claim 15 , wherein determining the number of errors in the second group of pages comprises using error correcting code (ECC) data to determine the number of errors.

18. The method of claim 17 , wherein the threshold for the number of errors is established in response to the number of errors that can be corrected using error correcting code (ECC).

19. An apparatus, comprising:
non-volatile memory comprising multiple blocks of memory cells, each block including multiple pages of memory cells; and
a controller coupled to the plurality of pages of non-volatile memory, the controller configured to perform operations comprising,
performing a first determination of the number of memory page reads of a first group of pages of the non-volatile memory, and determining that a number of memory page reads exceeds a page read threshold,
in response to determining that a number of memory page reads exceeds the first page read threshold, marking a first block of the non-volatile memory containing the first group of pages for refresh;
refreshing data stored in the first block,
performing a second determination of the number of memory page reads of a second group of pages of the non-volatile memory, and determining that the number of memory page reads does not exceed the page read threshold;
subsequent to determining that the number of memory page reads of the second group of pages does not exceed the page read threshold, reading data from some portion of the second group of pages to check the pages for errors,
determining that the number of errors in the read portion of the second group of pages exceeds an error threshold;
marking a second block of the non-volatile memory containing the second group of pages for refresh; and
refreshing data stored in the second block.

20. The apparatus of claim 19 , wherein the controller is further configured to store in memory the current block and page being checked for errors.

21. The

Assignees

• Micron Technology Inc

Inventors

• Blodgett Greg A

Classifications

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0727 Primary

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/1417

  Boot up procedures · CPC title