Data storage device capable of preventing a data retention fail of a nonvolatile memory device and operating method thereof

Patent metadata

Field	Value
Publication number	US-10102059-B2
Application number	US-201615146575-A
Country	US
Kind code	B2
Filing date	May 4, 2016
Priority date	Sep 25, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A method for operating a data storage device including a plurality of pages includes performing a read operation to a first page of the nonvolatile memory device according to a read voltage; adjusting the read voltage based on a number of error bits in the read-out data according to the read voltage; performing the read operation to the first page according to the adjusted read voltage; and performing a re-program operation to the first page based on a number of on cells as a result of the read operation according to the adjusted read voltage.

First claim

What is claimed is:

1. A data storage device comprising:
a nonvolatile memory device including a plurality of pages; and
a control unit suitable for:
selecting a first page for determining a retention fail among pages of a memory block which has a wear-leveling value smaller than an average,
controlling the nonvolatile memory device for performing a first read operation to the first page of the nonvolatile memory device according to a read voltage,
adjusting the read voltage based on a number of error bits in read-out data according to the read voltage when the retention fail is determined to occur in the first page,
performing a second read operation to the first page according to the adjusted read voltage to determine whether another retention fail is likely to occur in a re-program operation, and
performing the re-program operation to the first page based on a number of on cells as a result of the second read operation according to the adjusted read voltage.

2. The data storage device according to claim 1 , wherein the control unit controls the nonvolatile memory device to adjust the read voltage when the number of the error bits of the read-out data is equal to or larger than a first reference value.

3. The data storage device according to claim 1 , wherein the control unit controls the nonvolatile memory device to perform the re-program operation to the first page when the number of on cells is equal to or larger than a second reference value.

4. The data storage device according to claim 1 , wherein the control unit controls the nonvolatile memory device to perform the re-program operation by performing an error correction operation to the read-out data according to the read voltage and a program operation to error-corrected data.

5. The data storage device according to claim 4 , wherein the control unit controls the nonvolatile memory device to perform the program operation to the error-corrected data by programming the error-corrected data into the first page.

6. The data storage device according to claim 4 , wherein the control unit controls the nonvolatile memory device to perform the program operation to the error-corrected data by programming the error-corrected data into a second page.

7. The data storage device according to claim 1 , wherein the control unit controls the nonvolatile memory device to skip the re-program operation to the first page when the number of on cells is smaller than a second reference value.

8. The data storage device according to claim 1 , wherein the control unit controls the nonvolatile memory device to adjust the read voltage when the number of the error bits of the read-out data is equal to or larger than a first reference value and the error bits are correctable.

9. A method for operating a data storage device including a plurality of pages, the method comprising:
selecting a first page for determining a retention fail among pages of a memory block which has a wear-leveling value smaller than an average;
performing a first read operation to the first page of the nonvolatile memory device according to a read voltage;
adjusting the read voltage based on a number of error bits in read-out data according to the read voltage when the retention fail is determined to occur in the first page;
performing a second read operation to the first page according to the adjusted read voltage to determine whether another retention fail is likely to occur in a re-program operation; and
performing the re-program operation to the first page based on a number of on cells as a result of the second read operation according to the adjusted read voltage.

10. The method according to claim 9 , wherein the adjusting of the read voltage is performed when the number of the error bits of the read-out data is equal to or larger than a first reference value.

11. The method according to claim 9 , wherein the re-program operation to the first page is performed when the number of on cells is equal to or larger than a second reference value.

12. The method according to claim 9 , wherein the performing of the re-program operation includes performing an error correction operation to the read-out data according to the read voltage and a program operation to error-corrected data.

13. The method according to claim 12 , wherein the performing of the program operation to the error-corrected data includes programming the error-corrected data into the first page.

14. The method according to claim 12 , wherein the performing of the program operation to the error-corrected data includes programming the error-corrected data into a second page.

15. The method according to claim 9 , wherein the performing of the re-program operation to the first page includes skipping the re-program operation to the first page when the number of on cells is smaller than a second reference value.

16. The method according to claim 9 , wherein the adjusting of the read voltage is performed when the number of the error bits of the read-out data is equal to or larger than a first reference value and the error bits are correctable.

Assignees

• Sk Hynix Inc

Inventors

• Hong Ji Man

Classifications

• G06F11/142

  Reconfiguring to eliminate the error (group management mechanisms in a peer-to-peer network H04L67/1044) · CPC title

• G11C16/3495

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G06F11/106 Primary

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G06F2201/85

  Active fault masking without idle spares · CPC title