Nonvolatile memory and memory system

Patent metadata

Field	Value
Publication number	US-10796776-B2
Application number	US-201916429588-A
Country	US
Kind code	B2
Filing date	Jun 3, 2019
Priority date	Sep 3, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.

First claim

What is claimed is:

1. A nonvolatile memory comprising:
a memory cell array including a plurality of memory cells, each of the plurality of memory cells being configured to store data in accordance with a threshold voltage thereof; and
a control circuit configured to execute a first refresh process upon receiving a first command set,
wherein:
the first refresh process includes reprogramming at least one second memory cell among a plurality of first memory cells to which data has been programmed; and
in executing the first refresh process, the control circuit is configured to:
select the second memory cell from the plurality of first memory cells by verifying that a threshold voltage of the second memory cell is a voltage obtained by shifting a first voltage by a first correction amount in a case where the second memory cell has been programmed using the first voltage; and
select the second memory cell from the plurality of first memory cells by verifying that the threshold voltage of the second memory cell is a voltage obtained by shifting a second voltage by a second correction amount in a case where the second memory cell has been programmed using the second voltage.

2. The nonvolatile memory of claim 1 , wherein:
the first command set specifies first information including data associated with the first correction amount and the second correction amount; and
the control circuit is configured to select the second memory cell from the plurality of first memory cells by using the first information.

3. The nonvolatile memory of claim 2 , wherein:
the first command set further specifies second information including an address of the plurality of first memory cells and third information indicating data programmed to the plurality of first memory cells; and
the control circuit specifies locations of the plurality of first memory cells in the memory cell array based on the second information and executes the first refresh process for the second memory cell using the third information.

4. The nonvolatile memory of claim 3 , wherein, in executing the first refresh process, the control circuit is configured to:
reprogram the second memory cell using a third correction amount when the second memory cell is programmed using the first voltage; and
reprogram the second memory cell using a fourth correction amount when the second memory cell is programmed using the second voltage.

5. The nonvolatile memory of claim 4 , wherein:
the first command set further specifies fourth information indicating data associated with the third correction amount and the fourth correction amount; and
the control circuit is configured to execute the first refresh process for the second memory cell using the third information and the fourth information.

6. The nonvolatile memory of claim 3 , wherein:
the first command set further specifies fifth information indicating data associated with an upper limit of a number of program pulses to be applied to the second memory cell; and
in executing the first refresh process, the control circuit is configured to inhibit program pulses of the number which exceeds the upper limit from being applied to the second memory cell based on the fifth information.

7. The nonvolatile memory of claim 1 , wherein the first voltage corresponds to a first state and the second voltage corresponds to a second state, and wherein, in executing the first refresh process, the control circuit is configured to:
select at least one third memory cell to which data has been programmed using a third voltage corresponding to a third state different from the first state and the second state; and
select the second memory cell from the plurality of first memory cells excluding the selected third memory cell.

8. The nonvolatile memory of claim 7 , wherein the first refresh process includes inhibiting at least the third memory cell of the plurality of first memory cells from being reprogrammed.

9. The nonvolatile memory of claim 1 ,
wherein the memory cell array includes a plurality of groups, each of the plurality of groups includes a plurality of memory cells and is a unit of data programming,
wherein a first group among the plurality of groups includes the first memory cells.

10. A memory system comprising:
a nonvolatile memory including a plurality of blocks and a control circuit, each of the blocks including a plurality of groups and each of the groups including a plurality of memory cells; and
a memory controller configured to output a first command set to the nonvolatile memory to execute a first refresh process,
wherein:
the first refresh process includes reprogramming at least one second memory cell among a plurality of first memory cells to which data has been programmed, the plurality of first memory cells being in a first group in a first block; and
the memory controller is configured to:
determine to execute the first refresh process if the first group satisfies a first condition and a second condition; and
determine to execute a second refresh process if the first group satisfies the first condition and does not satisfy the second condition, the first condition including a condition that a first value of the first group exceeds a first threshold value, the second condition including a condition that a second value of the first group is not larger than a third threshold value.

11. The memory system of claim 10 , wherein the second refresh process includes relocating data in the first block to a second block.

12. The memory system of claim 11 , wherein the second block is a block in an erased state.

13. The memory system of claim 11 , wherein the second block is different from the first block.

14. The memory system of claim 10 , wherein the second refresh process includes erasing data from the first block after reading data out of the first block, and writing the read data to the first block.

15. The memory system of claim 10 , wherein:
the first condition includes a condition that a first value of the first group exceeds a first threshold value; and
the second condition includes a condition that the first value of the first group is not larger than a second threshold value larger than the first threshold value.

16. The memory system of claim 10 , wherein the second value includes a number of times of a read process of reading data out of the plurality of first memory cells executed until an error detected in the plurality of first memory cells is corrected.

17. The memory system of claim 10 , wherein the second value includes a number of memory cells included in the first memory cells having a threshold voltage within a predetermined range.

18. The memory system of claim 17 , wherein the predetermined range is set between peaks of adjacent two states among a plurality of states of threshold voltages formed by the plurality of first memory cells.

19. The memory system of claim 10 , wherein the second value includes a number of error bits of data read out of the plurality of first memory cells or an error correction result of data read out of the plurality of first memory cells.

20. The memory system of claim 19 , wherein the error bits are detected between adjacent two states among a plurality of states of threshold voltages formed by the first memory cells.

21. The memory system of claim 10 , wherein the second value includes a number of times of the first refresh process for the first group has been executed since the second refresh process for the first group is exe

Assignees

• Toshiba Memory Corp

Inventors

• Suzuki Riki
• Shirakawa Masanobu
• Kojima Yoshihisa
• Takada Marie
• Tokutomi Tsukasa

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/3431 Primary

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title