Integrated circuit including multiple height cell

Patent metadata

Field	Value
Publication number	US-12136626-B2
Application number	US-202117406157-A
Country	US
Kind code	B2
Filing date	Aug 19, 2021
Priority date	May 18, 2018
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first cell in a first row extending in a first direction;
a second cell in a second row extending in the first direction adjacent to the first row; and
a third cell continuously extending in the first row and the second row,
wherein the first cell comprises a plurality of first fins extending in the first direction and each configured to form a transistor of a first type or a transistor of a second type,
wherein the second cell comprises a plurality of second fins extending in the first direction and each configured to form a transistor of the first type or a transistor of the second type,
wherein the third cell comprises a plurality of third fins extending in the first direction in the first row and a plurality of fourth fins extending in the first direction in the second row,
wherein the plurality of third fins are configured to form a transistor of the first type, and
wherein the plurality of fourth fins are configured to form a transistor of the second type.

2. The integrated circuit of claim 1 , further comprising an interface cell continuously extending in the first row and the second row between the first cell and the third cell, and between the second cell and the third cell,
wherein the interface cell comprises an interconnection crossing a boundary between the first row and the second row.

3. The integrated circuit of claim 2 , wherein the interconnection comprises at least one of a contact, a gate line, or a metal pattern extending in a second direction perpendicular to the first direction.

4. The integrated circuit of claim 1 , wherein the first cell and the third cell are arranged adjacent to each other and share a gate line extending in a second direction perpendicular to the first direction at a boundary between the first cell and the third cell, the gate line being electrically connected to power lines configured to provide power to the first cell and the third cell, respectively.

5. The integrated circuit of claim 1 , wherein the third cell comprises at least one of an input pin or an output pin crossing a boundary between the first row and the second row.

6. The integrated circuit of claim 1 ,
wherein a number of the plurality of third fins is greater than a number of the plurality of first fins configured to form a transistor of the first type, and
wherein a number of the plurality of fourth fins is greater than a number of the plurality of second fins configured to form a transistor of the second type.

7. The integrated circuit of claim 6 , further comprising an interface cell continuously extending in the first row and the second row between the first cell and the third cell, and between the second cell and the third cell,
wherein, in the interface cell, the plurality of first fins and the plurality of third fins are separated from each other in the first direction, and the plurality of second fins and the plurality of fourth fins are separated from each other in the first direction.

8. The integrated circuit of claim 6 , further comprising an interface cell continuously extending in the first row and the second row between the first cell and the third cell, and between the second cell and the third cell,
wherein the interface cell comprises:
at least one fin aligned with at least one of the plurality of first fins and at least one of the plurality of third fins; and
at least one fin aligned with the at least one of the plurality of second fins and at least one of the plurality of third fins.

9. The integrated circuit of claim 1 ,
wherein the first cell and the second cell share a first power line extending in the first direction along a boundary between the first cell and the second cell; and
wherein the third cell comprises a second power line electrically connected to the first power line and extending in the first direction in the first row.

10. The integrated circuit of claim 9 , further comprising:
a first upper power line electrically connected to the first power line, the first upper power line extending in the first direction over the first power line; and
a second upper power line electrically connected to the second power line, the second upper power line extending in the first direction over the second power line.

11. The integrated circuit of claim 10 , wherein the first upper power line extends in the first direction across the third cell.

12. The integrated circuit of claim 10 , further comprising power mesh lines extending in a second direction perpendicular to the first direction over the first upper power line and the second upper power line,
wherein the power mesh lines comprise odd-numbered power mesh lines electrically connected to the first upper power line and even-numbered power mesh lines electrically connected to the second upper power line.

13. The integrated circuit of claim 9 , wherein the second power line has a dimension in a second direction that is equal to a dimension of the first power line in the second direction, the second direction being perpendicular to the first direction.

14. An integrated circuit comprising:
a first cell in a first row extending in a first direction;
a second cell in a second row extending in the first direction adjacent to the first row; and
a third cell continuously extending in the first row and the second row,
wherein the first cell and the third cell are configured to receive a first supply voltage from a first power line extending in the first direction,
wherein the first cell and the second cell are configured to receive a second supply voltage from a second power line extending in the first direction along a boundary between the first cell and the second cell,
wherein the second cell and the third cell are configured to receive the first supply voltage from a third power line extending the first direction,
wherein the third cell comprises a fourth power line electrically connected to the second power line and extending in the first direction, and
wherein a first distance between the first power line and the fourth power line is different from a second distance between the third power line and the fourth power line.

15. The integrated circuit of claim 14 ,
wherein the first cell comprises at least one fin configured to form a transistor of a first type and at least one fin configured to form a transistor of a second type,
wherein the second cell comprises at least one fin configured to form a transistor of the first type and at least one fin configured to form a transistor of the second type,
wherein the third cell comprises a plurality of third fins configured to form a transistor of the first type in the first row and a plurality of fourth fins configured to form a transistor of the second type in the second row.

16. An integrated circuit comprising:
a first cell in a first row extending in a first direction;
a second cell in a second row extending in the first direction adjacent to the first row;
a third cell in a third row extending in the first direction adjacent to the third second row;
a fourth cell continuously extending in the first row, the second row and the third row; and
an interface cell continuously extending in the first row, the second row and the third row between the first cell and the fourth cell, between the second cell and the fourth cell, and between the third cell and the fourth cell,
wherein the fourth cell comprises a plurality of first fins extending in the first direction in the first row and a first portion of the second row and configured to form a transistor of a first ty

Assignees

• Samsung Electronics Co Ltd

Inventors

• Do Jung-Ho
• Yu Ji-Su
• You Hyeon-Gyu
• Lee Seung-Young
• Lee Jae-Boong

Classifications

• H10D84/987

  Three levels of metal · CPC title

• H10D84/981

  Power supply lines · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D84/966

  Gate electrode terminals or contacts · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title