Power strap structure for high performance and low current density

Patent metadata

Field	Value
Publication number	US-9911697-B2
Application number	US-201615143842-A
Country	US
Kind code	B2
Filing date	May 2, 2016
Priority date	May 2, 2016
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced.

First claim

What is claimed is:

1. An integrated chip comprising:
an active area comprising a plurality of source/drain regions;
a middle-end-of-the-line (MEOL) structure contacting the active area and extending in a second direction;
a first metal wire layer comprising a first metal wire connected to the MEOL structure by a conductive contact, wherein the first metal wire extends in a first direction perpendicular to the second direction;
a power rail that extends in the first direction at a location laterally offset from the active area; and
a metal strap extending in the second direction and connected to the first metal wire by a first conductive via and to the power rail by a second conductive via.

2. The integrated chip of claim 1 , further comprising:
a plurality of gate structures arranged over the active area on opposing sides of the MEOL structure and extending in the second direction.

3. The integrated chip of claim 2 , wherein the active area continuously extends past two or more of the plurality of gate structures.

4. The integrated chip of claim 2 , further comprising:
a plurality of fins of semiconductor material extending outward from a semiconductor substrate, wherein the plurality of gate structures extend over the plurality of fins of semiconductor material.

5. The integrated chip of claim 1 , wherein the power rail is located on is the first metal wire layer, and the power rail is located at a location that is separated from the first metal wire by a dielectric material.

6. The integrated chip of claim 5 ,
wherein the MEOL structure laterally extends past the active area to a location vertically underlying the power rail; and
wherein the MEOL structure is connected to the power rail by a second conductive contact.

7. The integrated chip of claim 1 , wherein the power rail has a larger width than the first metal wire.

8. The integrated chip of claim 1 , wherein the second conductive via is arranged below the metal strap and is configured to connect the metal strap to the power rail, which is located on the first metal wire layer.

9. The integrated chip of claim 1 ,
wherein the power rail is over the first metal wire layer.

10. The integrated chip of claim 9 , further comprising:
a second MEOL structure adjacent to the MEOL structure and extending past the active area to a location that vertically underlies a second power rail arranged on the first metal wire layer, wherein the second MEOL structure is connected to the second power rail by a second conductive contact.

11. An integrated chip comprising:
an active area comprising a plurality of source/drain regions;
a plurality of middle-end-of-the-line (MEOL) structures contacting the active area and extending in a second direction;
a plurality of gate structures interleaved between the plurality of MEOL structures and extending in the second direction;
a first metal wire layer comprising a first metal wire connected to one or more of the plurality of MEOL structures by conductive contacts, wherein the first metal wire extends in a first direction perpendicular to the second direction;
a power rail extending in the first direction at a location laterally separated from the active area, wherein the power rail has a larger width than the first metal wire; and
a metal strap extending in the second direction and connected to the first metal wire by a first conductive via and to the power rail by a second conductive via.

12. The integrated chip of claim 11 , wherein the active area continuously extends past two or more of the plurality of gate structures.

13. The integrated chip of claim 11 , wherein the power rail is located on the first metal wire layer, and the power rail is located at a location that is separated from the first metal wire by a dielectric material.

14. The integrated chip of claim 13 ,
wherein the one or more of the plurality of MEOL structures laterally extend past the active area to a location vertically underlying the power rail; and
wherein the one or more of the plurality of MEOL structures are connected to the power rail by one or more second conductive contacts.

15. The integrated chip of claim 11 , wherein the power rail overlies the first metal wire layer.

16. The integrated chip of claim 15 , further comprising:
a second MEOL structure adjacent to the one or more of the plurality of MEOL structures and extending past the active area to a location that vertically underlies a second power rail arranged on the first metal wire layer, wherein the second MEOL structure is connected to the second power rail by a second conductive contact.

17. The integrated chip of claim 11 , wherein the active area comprises a plurality of fins of semiconductor material extending outward from a semiconductor substrate, wherein the plurality of gate structures extend over the plurality of fins of semiconductor material.

18. An integrated chip, comprising:
a source region and a drain region separated by a channel region;
a middle-end-of-the-line (MEOL) structure over the drain region;
a gate structure arranged over the channel region, wherein the MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure;
a first metal wire layer comprising a first metal wire located over the drain region and connected to the MEOL structure by a first conductive contact, and further comprising a power rail, wherein the power rail is laterally offset from the drain region; and
a second metal wire layer located over the first metal wire layer and comprising a metal strap that connects the first metal wire to the power rail.

19. The integrated chip of claim 18 ,
wherein the MEOL structure laterally extends past an outer boundary of the drain region to below the power rail; and
wherein the MEOL structure is connected to the power rail by a second conductive contact.

20. The integrated chip of claim 18 , further comprising:
a second MEOL structure over a second drain region, wherein the second MEOL structure is vertically disposed between the second drain region and the plane;
and
a second metal strap that is located on the second metal wire layer and that connects the first metal wire to the power rail.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih Liang
• Lai Chih Ming
• Young Charles Chew Yuen
• Yu Chi Yeh
• Tzeng Jiann Tyng
• Sio Kam Tou
• Sue Pin Dai
• Liu Ru Gun
• Peng Shih Wei
• Chen Wen Hao
• Yen Yung Sung
• Chen Chun Kuang

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/432

  comprising crossing interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title