Integrated circuit and method of forming an integrated circuit

Patent metadata

Field	Value
Publication number	US-10380315-B2
Application number	US-201715682885-A
Country	US
Kind code	B2
Filing date	Aug 22, 2017
Priority date	Sep 15, 2016
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

An IC structure includes a cell, a first rail and a second rail. The cell includes a first and a second active region and a first gate structure. The first and second active region extend in a first direction and is located at a first level. The second active region is separated from the first active region in a second direction. The first gate structure extends in the second direction, overlaps the first and second active region, and is located at a second level. The first rail extends in the first direction, overlaps the first active region, is configured to supply a first supply voltage, and is located at a third level. The second rail extends in the first direction, overlaps the second active region, is located at the third level, separated from the first rail in the second direction, and is configured to supply a second supply voltage.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
a first cell comprising:
a first active region extending in a first direction and being located at a first level;
a second active region extending in the first direction, being located at the first level, and being separated from the first active region in a second direction different from the first direction, and
a first gate structure extending in the second direction, overlapping the first active region and the second active region, and being located at a second level different from the first level;

a first rail extending in the first direction, overlapping the first active region, being configured to supply a first supply voltage, and being located at a third level different from the first level and the second level, and
a second rail extending in the first direction, overlapping the second active region, being located at the third level, being separated from the first rail in the second direction, and being configured to supply a second supply voltage different from the first supply voltage.

2. The integrated circuit structure of claim 1 , wherein the first cell further comprises:
a set of fins extending in the first direction and below the first gate structure, each fin of the set of fins being separated from an adjacent fin of the set of fins in the second direction by a fin pitch.

3. The integrated circuit structure of claim 1 , wherein the first cell further comprises:
a shallow trench isolation (STI) structure between the first active region and the second active region.

4. The integrated circuit structure of claim 1 , wherein at least the first rail overlaps a center of the first active region, or the second rail overlaps a center of the second active region.

5. The integrated circuit structure of claim 1 , wherein the first cell further comprises:
a first side;
a second side being an opposite side of the first cell from the first side;
a first dummy gate structure extending in the second direction and overlapping the first side, and
a second dummy gate structure extending in the second direction and overlapping the second side.

6. The integrated circuit structure of claim 1 , further comprising:
a set of vias over the first gate structure, a first via of the set of vias being separated from a second via of the set of vias in the second direction.

7. The integrated circuit structure of claim 1 , wherein
the first active region has a first dopant type, and
the second active region has a second dopant type different from the first dopant type.

8. The integrated circuit structure of claim 1 , further comprising:
a second cell adjacent to the first cell, the second cell comprising:
a third active region extending in the first direction and being located at the first level;
a fourth active region extending in the first direction, being located at the first level, and being separated from the third active region in the second direction;
a second gate structure extending in the second direction, overlapping the third active region and the fourth active region and being located at the second level;
a first side, and
a second side being an opposite side of the second cell from the first side,

wherein a center of the first active region is aligned with the first side of the second cell in the first direction, the first rail overlaps the first side of the second cell and the center of the first active region, and a height of the first cell is different from a height of the second cell.

9. The integrated circuit structure of claim 8 , further comprising:
a third rail extending in the first direction, overlapping the second side of the second cell, being configured to supply the second supply voltage, and being located at the third level.

10. The integrated circuit structure of claim 8 , wherein the second cell comprises:
a third side;
a fourth side being an opposite side of the second cell from the third side;
a first dummy gate structure extending in the second direction and overlapping the third side, and
a second dummy gate structure extending in the second direction and overlapping the fourth side.

11. A method of fabricating an integrated circuit structure, the method comprising:
placing a first cell layout pattern on a layout level, the first cell layout pattern corresponding to fabricating a first cell of the integrated circuit structure, the first cell layout pattern comprising a first side and a second side on an opposite side of the first cell from the first side, the placing the first cell layout pattern comprising:
placing a first active region layout pattern on a first layout level, the first active region layout pattern corresponding to fabricating a first active region of the integrated circuit structure, the first active region layout pattern extending in a first direction;
placing a second active region layout pattern on the first layout level, the second active region layout pattern corresponding to fabricating a second active region of the integrated circuit structure, the second active region layout pattern extending in the first direction and being separated from the first active region layout pattern in a second direction different from the first direction; and
placing a first gate layout pattern on a second layout level different from the first layout level, the first gate layout pattern corresponding to fabricating a first gate structure of the integrated circuit structure, the first gate layout pattern extending in the second direction, and overlapping the first active region layout pattern and the second active region layout pattern;

placing a first rail layout pattern on a third layout level different from the first layout level and the second layout level, the first rail layout pattern corresponding to fabricating a first rail of the integrated circuit structure, the first rail being configured to supply a first supply voltage, the first rail layout pattern extending in the first direction and overlapping the first active region layout pattern; and
placing a second rail layout pattern on the third layout level, the second rail layout pattern corresponding to fabricating a second rail of the integrated circuit structure, the second rail being configured to supply a second supply voltage different from the first supply voltage, the second rail layout pattern extending in the first direction, and being separated from the first rail layout pattern in the second direction, the second rail layout pattern not overlapping a first side or a second side of the first cell layout pattern,
wherein at least one of the above layout patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor; and
manufacturing the integrated circuit structure based on at least one of the above layout patterns of the integrated circuit structure.

12. The method of claim 11 , wherein the placing the first cell layout pattern further comprises:
placing a set of fin layout patterns on the layout level, the set of fin layout patterns corresponding to fabricating a set of fins of the integrated circuit structure, the set of fin layout patterns extending in the first direction and being below the first gate layout pattern, each of the layout patterns of the set of fin layout patterns being separated from an adjacent layout pattern of the set of fin layout patterns in the second direction by a fin pitch.

13. The method of claim 11 , wherein the placing the first cell layout pattern further comprises:
placing a first dummy gate layout pattern over a third side of the fir

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Zhuang hui-zhong
• Chiang Ting-Wei
• Lu Lee-Chung
• Tien Li-Chun
• Chen Shun Li

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/11807

  Electricity · mapped topic

• H01L2027/11881

  Electricity · mapped topic

• G06F17/5081 Primary

  Physics · mapped topic