Gate structure and method with enhanced gate contact and threshold voltage

Patent metadata

Field	Value
Publication number	US-12119403-B2
Application number	US-202318355997-A
Country	US
Kind code	B2
Filing date	Jul 20, 2023
Priority date	Nov 29, 2017
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

First claim

What is claimed is:

1. A method, comprising:
forming isolation features in a substrate, defining first fins in a first region and second fins in a second region;
forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins;
depositing an inter-layer dielectric (ILD) layer on the substrate;
removing the first and second dummy gate stacks by an etching process, resulting a first gate trench and a second gate trench in the ILD layer;
depositing a first tantalum titanium nitride layer in the first and second gate trenches;
depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench;
performing an etching process to the titanium aluminum nitride layer in the first gate trench while the second region is protected from the etching process;
depositing a second tantalum titanium nitride layer in the first gate trench; and
filling a low resistance metal in the first gate trench, thereby forming a first gate stack in the first gate trench and a second gate stack in the second gate trench.

2. The method of claim 1 , wherein the filling the low resistance metal in the first gate trench includes depositing one of tungsten, copper, aluminum, copper aluminum alloy and a combination thereof.

3. The method of claim 2 , prior to the performing an etching process to the titanium aluminum nitride layer in the first gate trench, further comprising forming a patterned mask to cover the second region and uncover the first region.

4. The method of claim 2 , wherein the performing of the etching process to the titanium aluminum nitride layer in the first gate trench includes partially removes the titanium aluminum nitride layer in the first gate trench.

5. The method of claim 1 , prior to the depositing of the first tantalum titanium nitride layer, further comprising depositing a high-k dielectric material layer in the first and second gate trenches.

6. The method of claim 1 , wherein the first gate stack includes a first segment on the first fins and a second segment being extended from the first fins onto a shallow trench isolation (STI) feature.

7. The method of claim 6 , wherein the second segment of the first gate stack includes the first and second tantalum titanium nitride layers with the titanium aluminum nitride layer interposed therebetween.

8. The method of claim 7 , wherein the first segment of the first gate stack defines a first air gap surrounded by the second tantalum titanium nitride layer while the second segment is free of void.

9. The method of claim 8 , wherein the second gate stack includes a third segment on the second fins and a fourth segment being extended from the second fins onto the STI feature.

10. The method of claim 9 , wherein the fourth segment of the second gate stack defines a second air gap surrounded by the first tantalum titanium nitride layer and the third segment of the second gate stack defines a third air gap surrounded by the first tantalum titanium nitride layer.

11. The method of claim 10 , wherein the third air gap in the third segment of the second gate stack has a volume being greater than that of the second air gap in the fourth segment of the second gate stack.

12. A method, comprising:
forming isolation features in a substrate, defining first fins in a first region and second fins in a second region;
forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins;
depositing an inter-layer dielectric (ILD) layer on the substrate;
removing the first and second dummy gate stacks by an etching process, resulting in a first gate trench and a second gate trench in the ILD layer;
depositing a high-k dielectric material layer in the first and second gate trenches;
depositing a first tantalum titanium nitride layer over the high-k dielectric material layer in the first and second gate trenches;
depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench;
performing an etching process to the titanium aluminum nitride layer in the first gate trench such that the titanium aluminum nitride layer in the first gate trench is recessed; and
filling a low resistance metal in the first gate trench, thereby forming a first gate stack in the first gate trench and a second gate stack in the second gate trench, and wherein the first and second gate stacks are different in structure.

13. The method of claim 12 , wherein the filling the low resistance metal in the first gate trench includes depositing one of tungsten, copper, aluminum, copper aluminum alloy and a combination thereof.

14. The method of claim 12 , prior to the filling a low resistance metal in the first gate trench, further comprising depositing a second tantalum titanium nitride layer on the recessed titanium aluminum nitride layer in the first gate trench.

15. The method of claim 14 , prior to the performing an etching process to the titanium aluminum nitride layer in the first gate trench, further comprising forming a patterned mask to cover the second region and uncover the first region.

16. The method of claim 14 , wherein
the first gate stack includes a first segment on the first fins and a second segment being extended from the first fins onto a shallow trench isolation (STI) feature;
the second segment of the first gate stack includes the first and second tantalum titanium nitride layers with the titanium aluminum nitride layer interposed therebetween; and
the first segment of the first gate stack defines a first air gap surrounded by the second tantalum titanium nitride layer while the second segment is free of void.

17. The method of claim 16 , wherein
the second gate stack includes a third segment on the second fins and a fourth segment being extended from the second fins onto the STI feature;
the fourth segment of the second gate stack defines a second air gap surrounded by the first tantalum titanium nitride layer;
the third segment of the second gate stack defines a third air gap surrounded by the first tantalum titanium nitride layer; and
the third air gap in the third segment of the second gate stack has a volume being greater than that of the second air gap in the fourth segment of the second gate stack.

18. A method, comprising:
forming isolation features in a substrate, defining first fins in a first region and second fins in a second region;
forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins;
depositing an inter-layer dielectric (ILD) layer on the substrate;
removing the first and second dummy gate stacks by an etching process, resulting a first gate trench and a second gate trench in the ILD layer;
depositing a high-k dielectric material layer in the first and second gate trenches;
depositing a first tantalum titanium nitride layer in the first and second gate trenches;
depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench;
performing an etching process to the titanium aluminum nitride layer in the first gate trench such that the titanium aluminum nitride layer is recessed while the second region is protected from the etching process;
depositing a second tantalum titanium nitride layer on the recessed titanium aluminum nitride layer in the first gate trench; and
filling a low resistance metal in the first gate trench, thereby forming a first gate stack is formed in the first gate tr

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Max
• Peng Yen-Ming
• Ho Wei-Shuo

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3444

  P-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title