High-k metal gate transistor structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2017162575-A1
Application number	US-201615337894-A
Country	US
Kind code	A1
Filing date	Oct 28, 2016
Priority date	Dec 7, 2015
Publication date	Jun 8, 2017
Grant date	—

Abstract

The present disclosure provides HKMG transistor structures and fabrication methods thereof. An exemplary method includes providing a base substrate having a first region and a second region; forming a dielectric layer having a first opening in the first region and a second opening in the second region over; forming a gate dielectric layer on a side surface of the first opening and a portion of the base substrate in the first opening and on a side surface of the second opening and a portion of the base substrate in the second opening; filling a sacrificial layer in the first opening; forming a second work function layer in the second opening and a second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming a first work function layer in the first opening and a first gate electrode layer on the first work function layer.

First claim

What is claimed is:

1 . A method for fabricating a high-K metal gate transistor structure, comprising:
providing a base substrate having a first region and a second region; forming a dielectric layer having a first opening exposing a first surface portion of the base substrate in the first region and a second opening exposing a second surface portion of the base substrate in the second region over the base substrate; forming a gate dielectric layer on a side surface of the first opening and the first surface portion of the base substrate in the first opening and on a side surface of the second opening and the second surface portion of the base substrate in the second opening; filling a sacrificial layer in the first opening; forming a second work function layer in the second opening and a second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming a first work function layer in the first opening and a first gate electrode layer on the first work function layer.

2 . The method according to claim 1 , wherein the base substrate comprises:
a semiconductor substrate having a surface; a plurality of fins formed on the surface of the semiconductor substrate in the first region and the second region; and an isolation layer covering side surfaces of the fins and with a top surface lower than top surfaces of the fins.

3 . The method according to claim 2 , wherein:
the first opening crosses over the fins in the first region and exposes side and top surfaces of portions of the fins in the first region; and the second opening crosses over the fins in the second region and exposes side and top surfaces of portions of the fins in the second region.

4 . The method according to claim 3 , wherein:
the gate dielectric layer is formed on the side and top surfaces of the fins exposed by the first opening and the second opening.

5 . The method according to claim 1 , after forming the sacrificial layer, further comprising:
forming a cap layer made of TiN on a surface of the dielectric layer.

6 . The method according to claim 1 , before forming the sacrificial layer, further comprising:
performing a thermal annealing process.

7 . The method according to claim 6 , before forming the sacrificial layer, further comprising:
forming a first barrier layer made of TaN on the cap layer.

8 . The method according to claim 1 , wherein:
the sacrificial layer is made of one of a back anti-reflective material, a deep UV light absorption material, and an organic dielectric material.

9 . The method according to claim 1 , wherein forming the sacrificial layer comprises:
forming a sacrificial film on a surface of the dielectric layer and filling the first opening and the second opening; planarizing the sacrificial film to remove a portion of the sacrificial film above the surface of the dielectric layer; and removing the sacrificial layer in the second opening.

10 . The method according to claim 1 , wherein forming the second work function layer and the second gate electrode layer comprises:
forming a second work function film on the gate dielectric layer and the sacrificial layer; forming a second gate dielectric film on the second work function film; and planarizing the second gate dielectric film and the second work function film to remove portions of the second gate dielectric film and the second work function film higher than the dielectric layer.

11 . The method according to claim 1 , wherein forming the first work function layer and the first gate electrode layer comprises:
forming a first work function film on the gate dielectric layer, the dielectric layer and the second gate electrode layer; forming a first gate electrode film on the first work function film and filling the first opening; planarizing the first gate electrode film and the first work function film until the surface of the dielectric layer is exposed.

12 . The method according to claim 11 , after forming the first work function film, further comprising:
forming a second barrier film on the first work function film; forming the first gate dielectric film on the second barrier film; and forming a second barrier layer in the first opening.

13 . The method according to claim 12 , wherein:
the second barrier layer is made of TiN.

14 . The method according to claim 11 , wherein the first opening and the second opening are formed by:
forming dummy gate structures having a dummy gate electrode layer on the base substrate in the first region and the second region; respectively; forming the dielectric layer having a surface level with a top surface of the dummy gate electrode layer; and removing the dummy gate electrode layer to form the first opening in the dielectric layer in the first region and the second opening in the dielectric layer in the second region.

15 . The method according to claim 14 , before forming the dielectric layer, further comprising:
forming source/drain regions in the base substrate at the two sides of the gate dummy gate structures.

16 . A high-K metal gate (HKMG) transistor structure, comprising:
a semiconductor substrate having a first region and a second region; a plurality of fins formed on the semiconductor substrate in the first region and the second region; a first HKMG structure formed over the fins in the first region; a second HKMG structure formed over the fins in the second region; source/drain regions formed in the fins at the two sides of the HKMG structures; an isolation layer formed between adjacent fins; and a dielectric layer covering side surfaces of the HKMG structures formed on the semiconductor substrate, the source/drain regions and the isolation layer.

17 . The high-K metal gate transistor structure according to claim 16 , wherein:
the first HKMG structure includes a gate dielectric layer, a first work function layer, and a first gate electrode layer; and the second HKMG structure includes a gate dielectric layer, a second work function layer, and a second gate electrode layer.

18 . The high-K metal gate transistor structure according to claim 17 , wherein the first HKMG structure and the second HKMG structure are formed by:
forming a first opening exposing a portion of a surface of the semiconductor substrate and the fins in the first region and a second opening exposing a portion of the surface of the semiconductor substrate and the fins in the second region; forming a gate dielectric layer on a side surface of the first opening and the exposed surfaces of the semiconductor substrate and the fins in the first opening and on a side surface of the second opening and the exposed surfaces of the semiconductor substrate and the fins in the second opening; filling a sacrificial layer in the first opening; forming the second work function layer in the second opening and the second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming the first work function layer in the first opening and the first gate electrode layer on the work function layer.

19 . The high-K metal gate transistor structure according to claim 17 , wherein:
the first region is an NMOS regions; the second region is a PMOS region; the first work function layer is made of TiAlC; the second work function layer is made of TiN; the first gate electrode layer is made of one of TiAl and W; and the second gate electrode layer is made of W.

20 . The high-K metal g

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp
• Simiconductor Mfg Int (Beijing) Corp

Inventors

• Li Yong

Classifications

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title