Strain enhanced SiC power semiconductor device and method of manufacturing

Patent metadata

Field	Value
Publication number	US-12113131-B2
Application number	US-202017633804-A
Country	US
Kind code	B2
Filing date	Aug 7, 2020
Priority date	Aug 9, 2019
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.

First claim

The invention claimed is:

1. A SiC transistor device comprising:
a SiC semiconductor substrate having a top surface and a bottom surface;
a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface;
a source structure formed in the top surface of the SiC epitaxial layer, the source structure having a top surface;
a source contact structure electrically coupled to the top surface of the source structure;
a gate structure including a gate dielectric, a metal gate, and a gate insulation;
a first backside metal contact on the bottom surface of the SiC semiconductor substrate;
a stress inducing layer on the first backside metal contact; and
a second backside metal contact on the stress inducing layer.

2. The SiC transistor device according to claim 1 , wherein the second backside metal contact comprises at least one of titanium, nickel, aluminum or silver.

3. The SiC transistor device according to claim 1 , further comprising a second stress inducing layer on the gate structure.

4. The SiC transistor device according to claim 1 , further comprising a structured and electrically insulating second stress inducing layer on the top surface of the SiC epitaxial layer.

5. The SiC transistor device according to claim 1 , further comprising a second stress inducing layer on the gate structure.

6. The SiC transistor device according to claim 1 , wherein the stress inducing layer induces a tensile or compressive stress in a range of 500 MPa to 2000 MPa.

7. The SiC transistor device according to claim 1 , further comprising a structured and electrically insulating stress inducing layer on the top surface of the SiC epitaxial layer, wherein the source contact structure is electrically coupled to the top surface of the source structure through the structured and electrically insulating stress inducing layer.

8. The SiC transistor device according to claim 7 , wherein the structured and electrically insulating stress inducing layer induces a tensile or compressive stress in a range of 500 MPa to 2000 MPa.

9. The SiC transistor device according to claim 1 , further comprising a first contact layer electrically contacting the source contact structure and a second contact layer electrically contacting the metal gate, wherein the first contact layer or the second contact layer is at least partially covered with a passivation layer.

10. The SiC transistor device according to claim 1 , wherein the SiC semiconductor substrate and the SiC epitaxial layer are both a 4H-SiC of n-type.

11. The SiC transistor device according to claim 1 , wherein the stress inducing layer has a thickness between about 1 nm and 1000 nm.

12. The SiC transistor device according to claim 1 , wherein the stress inducing layer comprises silicon nitride.

13. The SiC transistor device according to claim 1 , wherein the stress inducing layer comprises titanium nitride.

14. The SiC transistor device according to claim 1 , wherein the SiC transistor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).

15. The SiC transistor device according to claim 1 , wherein the SiC transistor device is an insulated-gate bipolar transistor (IGBT).

16. A method of manufacturing a SiC transistor device comprising:
forming a SiC semiconductor substrate having a top surface and a bottom surface;
forming epitaxially a SiC epitaxial layer on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface;
forming a source structure in the top surface of the SiC epitaxial layer, the source structure having a top surface;
forming a source contact structure electrically coupled to the top surface of the source structure;
forming a gate structure on the top surface of the SiC epitaxial layer, wherein the gate structure includes a gate dielectric and a metal gate;
forming a first backside metal contact on the bottom surface of the SiC semiconductor substrate;
forming a stress inducing layer on the first backside metal contact;
structuring the stress inducing layer; and
forming a second backside metal contact on the structured stress inducing layer.

17. The method according to claim 16 , further comprising forming a stress inducing layer at the gate structure.

18. The method according to claim 16 , further comprising forming an electrically insulating stress inducing layer on the top surface of the SiC epitaxial layer and structuring the electrically insulating stress inducing layer, wherein the source contact structure is electrically coupled to the top surface of the source structure through the structured electrically insulating stress inducing layer and the gate structure is formed on the electrically insulating stress inducing layer.

19. The method according to claim 16 , further comprising forming a first contact layer electrically contacting the source contact structure and forming a second contact layer electrically contacting the metal gate.

20. A method of manufacturing a SiC transistor device comprising:
forming a SiC semiconductor substrate having a top surface and a bottom surface;
forming epitaxially a SiC epitaxial layer on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface;
forming a source structure in the top surface of the SiC epitaxial layer, the source structure having a top surface;
forming an electrically insulating first stress inducing layer on the top surface of the SiC epitaxial layer;
structuring the electrically insulating first stress inducing layer;
forming a source contact structure electrically coupled to the top surface of the source structure;
forming a gate structure on the top surface of the SiC epitaxial layer, wherein the gate structure includes a metal gate;
forming a first backside metal contact on the bottom surface of the SiC semiconductor substrate;
forming a second stress inducing layer on the first backside metal contact;
structuring the second stress inducing layer; and
forming a second backside metal contact on the structured second stress inducing layer.

Assignees

• Hitachi Energy Ltd

Inventors

• Wirths Stephan
• Knoll Lars

Classifications

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D30/798

  being provided in or under the channel regions · CPC title