Electric field management in semiconductor devices

Patent metadata

Field	Value
Publication number	US-12106960-B2
Application number	US-202117504391-A
Country	US
Kind code	B2
Filing date	Oct 18, 2021
Priority date	Oct 18, 2021
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

Electric field management techniques in GaN based semiconductors that utilize patterned regions of differing conductivity under the active GaN device, such as a GaN high electron mobility transistor (HEMT), are described. As an example, a patterned layer of oxidized silicon can be formed superjacent a layer of silicon dioxide during or prior to the heteroepitaxy of GaN or another semiconductor material. These techniques can be useful for back-side electric field management because a silicon layer, for example, can be made conductive to act as a back-side field plate.

First claim

The claimed invention is:

1. A compound semiconductor heterostructure transistor device comprising:
an insulator layer formed over a substrate;
a crystal lattice layer formed over the insulator layer, wherein the crystal lattice layer has been oxidized and includes a first portion and a second, etched away portion, and wherein the crystal lattice layer is implanted with a material; and
a first semiconductor material layer formed over a second semiconductor material layer to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel, wherein the 2DEG channel is more conductive than either the first semiconductor material layer or the second semiconductor material layer, and wherein the second semiconductor material layer is formed over the crystal lattice layer;
a gate contact in contact with the first semiconductor material layer; and
drain and source contacts in contact with the first semiconductor material layer or the 2DEG channel,
a backside field plate including the first portion of the crystal lattice layer, wherein the first portion extends laterally from a region underlying the source contact to a region between the gate contact and the drain contact.

2. The compound semiconductor heterostructure transistor device of claim 1 , wherein the crystal lattice layer includes a silicon layer.

3. The compound semiconductor heterostructure transistor device of claim 1 , wherein the insulator layer includes a silicon dioxide layer.

4. The compound semiconductor heterostructure transistor device of claim 1 , wherein the implanted material includes a dopant to adjust a conductivity of the crystal lattice layer.

5. The compound semiconductor heterostructure transistor device of claim 4 , wherein the dopant includes at least one of boron, nitrogen, or aluminum.

6. The compound semiconductor heterostructure transistor of claim 1 , wherein the implanted material includes oxygen to adjust a concentration of the oxygen at an interface between the insulator layer and the crystal lattice layer.

7. The compound semiconductor heterostructure transistor of claim 1 , wherein the second semiconductor material layer includes gallium nitride, and wherein the first semiconductor material layer includes aluminum gallium nitride.

8. A compound semiconductor heterostructure transistor device comprising:
an insulator layer formed over a substrate;
a silicon layer formed over the insulator layer, wherein the silicon layer has been oxidized and includes a first portion and a second, etched away portion, and wherein the silicon layer is implanted with a material; and
a first semiconductor material layer formed over a second semiconductor material layer to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel, wherein the 2DEG channel is more conductive than either the first semiconductor material layer or the second semiconductor material layer, and wherein the second semiconductor material layer is formed over the silicon layer;
a gate contact in contact with the first semiconductor material layer; and
drain and source contacts in contact with the first semiconductor material layer or the 2DEG channel,
a backside field plate including the first portion of the silicon layer, wherein the first portion extends laterally from a region underlying the source contact to a region between the gate contact and the drain contact.

9. The compound semiconductor heterostructure transistor device of claim 8 , wherein the silicon layer is implanted with a dopant to adjust a conductivity of the silicon layer.

Assignees

• Analog Devices Inc

Inventors

• Fiorenza James G
• Piedra Daniel

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3822 Primary

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title