Apparatus and method of fabrication for GaN/Si transistors isolation

Patent metadata

Field	Value
Publication number	US-9793389-B1
Application number	US-201615182667-A
Country	US
Kind code	B1
Filing date	Jun 15, 2016
Priority date	Jun 15, 2016
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

In one embodiment, a method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit is provided. The method comprises providing a silicon on insulator (SOI) wafer and fabricating an isolated first silicon region and an isolated second silicon region on the SOI wafer wherein each of the first silicon region and the second silicon region is bounded on its sides by a trench filled with insulator material. The method further comprises fabricating an active area comprising GaN on each of the first silicon region and the second silicon region to form the first transistor circuit and the second transistor circuit and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit, the method comprising:
providing a silicon on insulator (SOI) wafer comprising an insulator layer and a silicon layer disposed over the insulator layer;
applying a first mask to the silicon layer;
etching the first mask and the silicon layer to an etch stop at the insulator to form an isolated first silicon region and an isolated second silicon region each disposed over the insulator layer, the isolated first and second silicon regions being separated from one another by a trench;
filling the trench with insulator material so as to bound each of the first silicon region and the second silicon region on its respective sides by the insulator material;
after filling the trench, removing the first mask to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region;
after removing the first mask, fabricating a first active area comprising gallium nitride (GaN) within the first cavity over the isolated first silicon region and a second active area comprising GaN within the second cavity over the isolated second silicon region to respectively form the first transistor circuit and the second transistor circuit; and
fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.

2. The method of claim 1 wherein fabricating the first active area comprises fabricating through epitaxial growth a first GaN layer on the isolated first silicon region and fabricating through epitaxial growth a first aluminum gallium nitride (AlGaN) layer on the first GaN layer; and
wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN layer on the second GaN layer.

3. The method of claim 1 wherein the fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit comprises:
fabricating the body connection for each of the first transistor circuit and the second transistor circuit; and
fabricating the source, drain, and gate connection for each of the first transistor circuit and the second transistor circuit after fabricating the body connection.

4. The method of claim 1 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises:
applying a second mask above the wafer;
etching a first via hole through the second mask and the first active area of the first transistor circuit to the isolated first silicon region, the first via hole having a first sidewall;
etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall;
respectively coating the first and second sidewalls with insulator material; and
after the coating, implanting metal material into each of the first and second via holes to form a respective contact to the isolated first and second silicon regions.

5. The method of claim 1 wherein fabricating the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit comprises:
applying a second mask above the wafer;
patterning the second mask for contact holes;
depositing metal material into the contact holes to form contacts for the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit; and
removing the second mask.

6. The method of claim 5 further comprising:
depositing inter-layer-dielectric (ILD) material above the wafer;
patterning the ILD material for metal interconnects;
depositing metal and polishing to form interconnects.

7. The method of claim 1 , further comprising
fabricating through deposition and polishing a passivation layer above each of the isolated first silicon region and the isolated second silicon region.

8. The method of claim 7 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises:
applying a second mask above the wafer;
etching a first via hole through the second mask and the first active area of the first transistor circuit to the isolated first silicon region, the first via hole having a first sidewall;
etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall;
respectively coating the first and second sidewalls with insulator material; and
after the coating, implanting metal material into each of the first and second via holes to form a respective contact to the isolated first and second silicon regions.

9. The method of claim 8 wherein fabricating the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit comprises:
applying a third mask above the wafer;
patterning the third mask for contact holes;
depositing metal material into the contact holes to form contacts for the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit; and
removing the third mask.

10. A method of fabricating gallium nitride (GaN) transistors on a silicon on insulator (SOI) wafer with a GaN transistor in a first transistor circuit having its substrate isolated from the substrate of a transistor in a second transistor circuit, the method comprising:
fabricating an isolated first silicon region and an isolated second silicon region on a SOI wafer comprising an insulator layer and a silicon layer disposed over the insulator layer, each of the first silicon region and the second silicon region bounded on its sides by a trench filled with insulator material so as to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region;
fabricating a first active area within the first cavity over the isolated first silicon region and fabricating a second active area within the second cavity over the isolated second silicon region through epitaxial growth operations to respectively form the first transistor circuit and the second transistor circuit, the first active area comprising a first GaN layer; and
fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.

11. The method of claim 10 wherein fabricating the isolated first silicon region and an isolated second silicon region on the SOI wafer comprises:
applying a mask to the silicon layer;
etching the mask and the silicon layer to an etch stop at the insulator layer to form a trench in the silicon layer separating the isolated first and second silicon regions from one another;
filling the trench with insulator material; and
removing the mask to define the first cavity and the second cavity.

12. The method of claim 10 wherein fabricating the first active area comprises fabricating through epitaxial growth a first GaN layer on the isolated first silicon region and fabricating through epitaxial growth a first aluminum gallium nitride (AlGaN) layer on the first GaN layer; and
wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN laye

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chern Chan-Hong
• Tsai Chun-Lin
• Chen Mark
• Wong King-Yuen

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title