High-voltage gallium nitride schottky diode

Patent metadata

Field	Value
Publication number	US-9735292-B2
Application number	US-201615055791-A
Country	US
Kind code	B2
Filing date	Feb 29, 2016
Priority date	Aug 28, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A Schottky diode is formed on a silicon support. A non-doped GaN layer overlies the silicon support. An AlGaN layer overlies the non-doped GaN layer. A first metallization forming an ohmic contact and a second metallization forming a Schottky contact are provided in and on the AlGaN layer. First vias extend from the first metallization towards the silicon support. Second vias extend from the second metallization towards an upper surface.

First claim

The invention claimed is:

1. A Schottky diode comprising, in the following order between a lower surface and an upper surface:
a doped silicon support;
a non-doped silicon layer;
a buffer layer;
a non-doped GaN layer; and
an AlGaN layer; and
further including:
a first metallization extending through the AlGaN layer forming an ohmic contact;
a second metallization on the AlGaN layer forming a Schottky contact;
a first via extending from the first metallization towards the lower surface and passing through the non-doped GaN layer, the buffer layer and the non-doped silicon layer; and
a second via extending from the second metallization towards the upper surface.

2. The Schottky diode of claim 1 , wherein the first and second metallizations each form a periodically repeated pattern.

3. The Schottky diode of claim 1 , further comprising, between the doped silicon support and the non-doped silicon layer, a silicon oxide layer, and wherein said first via further extends passing through the silicon oxide layer.

4. The Schottky diode of claim 1 , wherein the first via extends to make contact with a top of the doped silicon support.

5. The Schottky diode of claim 1 , wherein the second metallization comprises periodically repeated first islands.

6. The Schottky diode of claim 5 , wherein the first metallization forms a honeycomb network including a plurality of openings, and said first islands are positioned within said plurality of openings.

7. The Schottky diode of claim 5 , wherein the first metallization comprises periodically repeated second islands.

8. The Schottky diode of claim 7 , wherein the first islands and the second islands form a checkerboard pattern.

9. The Schottky diode of claim 1 , wherein the buffer layer is on and in direct contact with the non-doped silicon layer, and wherein the non-doped GaN layer is on and in direct contact with the buffer layer.

10. A Schottky diode, comprising:
a silicon on insulator substrate having a semiconductor support, an insulator layer on the semiconductor support and a semiconductor layer on the insulator layer;
an AlGaN layer over the silicon on insulator substrate;
a non-doped silicon layer between the semiconductor layer and the AlGaN layer;
a non-doped GaN layer between the non-doped silicon layer and the AlGaN layer;
a first metallization pattern extending through the AlGaN layer forming an ohmic contact;
a second metallization pattern on the AlGaN layer forming a Schottky contact;
first vias extending from a bottom of the first metallization pattern through the non-doped GaN layer, the non-doped silicon layer, the semiconductor layer and the insulator layer to contact the semiconductor support; and
second vias extending from a top of the second metallization pattern through a further insulating layer overlying the first and second metallization patterns.

11. The Schottky diode of claim 10 , further comprising an aluminum nitride layer between the non-doped silicon layer and the non-doped GaN layer, said first vias further passing through said aluminum nitride layer.

12. The Schottky diode of claim 11 , wherein the aluminum nitride layer is on and in direct contact with the non-doped silicon layer and the non-doped GaN layer is on and in direct contact with the aluminum nitride layer.

13. The Schottky diode of claim 10 , wherein the first and second metallization patterns form interleaved strips.

14. The Schottky diode of claim 10 , wherein the first metallization pattern forms hexagons and the second metallization pattern forms islands within the hexagons.

15. The Schottky diode of claim 10 , wherein the first and second metallization patterns form islands arranged in a checkerboard pattern.

16. A Schottky diode, comprising:
a bulk semiconductor substrate;
a non-doped semiconductor layer on the bulk semiconductor substrate;
a plurality of doped regions within the non-doped semiconductor layer;
an AlGaN layer over the non-doped semiconductor layer;
a first metallization pattern extending through the AlGaN layer forming an ohmic contact;
a second metallization pattern on the AlGaN layer forming a Schottky contact;
first vias extending from a bottom of the first metallization pattern to contact the doped regions of the non-doped semiconductor layer; and
second vias extending from a top of the second metallization pattern through an insulating layer overlying the first and second metallization patterns.

17. The Schottky diode of claim 16 , further comprising an aluminum nitride layer between the non-doped semiconductor layer and the AlGaN layer, said first vias further passing through said aluminum nitride layer.

18. The Schottky diode of claim 16 , further comprising a non-doped GaN layer between the non-doped semiconductor layer and the AlGaN layer, said first vias further passing through said non-doped GaN layer.

19. The Schottky diode of claim 16 , wherein the first and second metallization patterns form interleaved strips.

20. The Schottky diode of claim 16 , wherein the first metallization pattern forms hexagons and the second metallization pattern forms islands within the hexagons.

21. The Schottky diode of claim 16 , wherein the first and second metallization patterns form islands arranged in a checkerboard pattern.

22. The Schottky diode of claim 16 , wherein plurality of doped regions have a same thickness as the non-doped semiconductor layer and contact a top of the bulk semiconductor substrate.

23. The Schottky diode of claim 16 , further including a buffer layer on and in direct contact with the non-doped semiconductor layer.

Assignees

• St Microelectronics Tours Sas

Inventors

• Yvon Arnaud

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/0207

  Electricity · mapped topic

• H01L27/0814

  Electricity · mapped topic

• H01L29/417

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic