Methods of fabricating complementary gallium nitride integrated circuits

Patent metadata

Field	Value
Publication number	US-9978852-B2
Application number	US-201615251114-A
Country	US
Kind code	B2
Filing date	Aug 30, 2016
Priority date	Aug 12, 2013
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

An embodiment of a complementary GaN integrated circuit includes a GaN layer with a first bandgap. A second layer with a second bandgap is formed on the GaN layer, resulting in a 2DEG in a contact region between the GaN layer and the second layer. The second layer has a relatively thin portion and a relatively thick portion. A third layer is formed over the relatively thick portion of the second layer. The third layer has a third bandgap that is different from the second bandgap, resulting in a 2DHG in a contact region between the second layer and the third layer. A transistor of a first conductivity type includes the 2DHG, the relatively thick portion of the second layer, and the third layer, and a transistor of a second conductivity type includes the 2DEG and the relatively thin portion of the second layer.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit, the method comprising the steps of:
providing a first gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region;
forming a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub-layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer;
physically damaging a structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer to suppress the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer;
forming a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer;
forming a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer
forming first and second current carrying contacts over the first portion of the first sub-layer;
forming a first channel control contact over the first portion of the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type;
forming third and fourth current carrying contacts over the third layer;
forming a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type;
coupling a positive input terminal to the first current carrying terminal of the first transistor, wherein the positive input terminal is configured to receive a first voltage from a voltage source;
coupling a negative input terminal to the fourth current carrying terminal of the second transistor, wherein the negative input terminal is configured to receive a second voltage from the voltage source;
coupling a first transistor control terminal to the first channel control contact of the first transistor, wherein the first transistor control terminal is configured to receive a first switch control signal from a controller;
coupling a second transistor control terminal to the second channel control contact of the second transistor, wherein the second transistor control terminal is configured to receive a second switch control signal from a controller;
coupling a first cathode of a first diode to the first current carrying contact of the first transistor;
coupling a first anode of the first diode to the second current carrying contact of the first transistor;
coupling a second cathode of a second diode to the third current carrying contact of the second transistor;
coupling a second anode of the second diode to the fourth current carrying contact of the second transistor; and
coupling an output terminal to the second current carrying contact and the third current carrying contact to form an inverter, wherein the output terminal is configured to provide an AC signal to a load.

2. The method of claim 1 , wherein physically damaging the structure of the contact region comprises performing an ion implantation process to implant ions through the second portion of the first sub-layer over the second region and into the contact region, wherein the ion implantation forms traps that suppress the 2DEG in the second region.

3. The method of claim 2 , wherein performing the ion implantation process comprises:
applying mask material on the first sub-layer over the first region of the GaN layer;
implanting the ions through an opening in the mask material over the second portion of the first sub-layer.

4. The method of claim 2 , wherein performing the ion implantation process comprises:
implanting ions selected from oxygen (O), argon (Ar), and other ions having non-charge-producing characteristics.

5. The method of claim 2 , wherein performing the ion implantation process comprises:
implanting ions selected from magnesium (Mg), carbon (C), and other ions having charge-producing characteristics.

6. The method of claim 1 , wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAlN) alloy, and an indium gallium nitride (InGaN) alloy.

7. The method of claim 1 , wherein the first and second sub-layers are formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.

8. The method of claim 1 , wherein the first height is in a range of 15 nanometers to 30 nanometers.

9. The method of claim 8 , wherein the second height is in a range of 40 nanometers to 100 nanometers.

10. The method of claim 1 , wherein the third layer includes a semiconductor material doped with a p-type dopant.

11. The method of claim 1 , wherein the third layer has a thickness in a range of 10 nm to 30 nm.

12. The method of claim 1 , further comprising:
forming an isolation structure between the first transistor and the second transistor, wherein the isolation structure is selected from an isolation mesa, an implant region, and implant well, and a trench isolation structure.

13. A method of fabricating an integrated circuit, the method comprising the steps of:
providing a first gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region;
forming a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub-layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer;
physically damaging a structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer to suppress the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer;
forming a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN la

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Renaud Philippe

Classifications

• H10P30/206

  into Group III-V semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title