GaN-on-Si semiconductor device structures for high current/ high voltage lateral GaN transistors and methods of fabrication thereof

Patent metadata

Field	Value
Publication number	US-10283501-B2
Application number	US-201715447200-A
Country	US
Kind code	B2
Filing date	Mar 2, 2017
Priority date	Mar 3, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

First claim

The invention claimed is:

1. A wafer scale nitride semiconductor device structure comprising:
a silicon substrate having formed thereon a GaN epi-layer stack for a plurality of GaN die, said plurality of GaN die being arranged as an array with dicing streets therebetween;
each GaN die comprising:
a part of the GaN epi-layer stack, the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two dimensional electron gas (2DEG) active layer for a lateral GaN transistor;
source, drain and gate electrodes of the lateral GaN transistor being provided on a front-side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of each GaN die, and an overlying interconnect structure, comprising metallization and dielectric layers, defining respective source, drain and gate connections and contact areas; and

a trench structure formed around a periphery of each GaN die in said inactive area, the trench structure comprising a trench etched through layers of the overlying interconnect structure, through the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below an interface between the silicon substrate and the GaN epi-layer stack;
the trench structure further comprising a trench cladding, the trench cladding comprising a metal layer and an overlying passivation layer, the trench cladding extending over inner sidewalls of the trench and sealing exposed surfaces of layers of the overlying interconnect structure, layers of the GaN epi-layer stack, and the interface of the GaN epi-layer stack and the silicon substrate, wherein the metal layer of the trench cladding is conductive and connects the silicon substrate to a source contact area of the lateral GaN transistor.

2. The device structure of claim 1 , wherein the trench structure is laterally spaced from the dicing street.

3. The device structure of claim 1 , wherein the trench structure is laterally spaced from a scribe line of the dicing street.

4. The device structure of claim 1 , wherein the trench structure extends across the dicing street between adjacent GaN die.

5. The device of claim 1 , wherein the GaN die further comprises a seal ring formed over the inactive region of the GaN epi-layer stack and surrounding the lateral GaN transistor, the trench structure being formed between the seal ring and the dicing street, and wherein the metal layer of the trench cladding connects the silicon substrate to a metallization layer of the seal ring.

6. A nitride semiconductor device comprising:
a GaN die comprising:
a silicon substrate and a GaN epi-layer stack formed thereon comprising a GaN/AlGaN hetero-layer structure defining a two dimensional electron gas (2DEG) active layer for a lateral GaN transistor;
source, drain and gate electrodes of the lateral GaN transistor being provided on a front-side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of each die; and an overlying interconnect structure, comprising metallization and dielectric layers, defining respective source, drain and gate connections and contact areas;

a trench structure formed around a periphery of the GaN die, the trench structure comprising a trench etched through layers of the overlying interconnect structure, through layers of the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below the interface between the silicon substrate and the GaN epi-layer stack;
the trench structure further comprising a trench cladding, the trench cladding comprising a conductive metal layer and an overlying passivation layer, the trench cladding extending over inner sidewalls of the trench and sealing exposed surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack, and the interface of the GaN epi-layer stack and the silicon substrate, wherein the conductive metal layer of the trench cladding connects the silicon substrate to a source contact area of the lateral GaN transistor.

7. The device of claim 6 , wherein the trench structure is laterally spaced from edges of the GaN die.

8. The device of claim 6 , wherein the trench structure extends to edges of the GaN die.

9. The device of claim 6 , wherein the GaN die further comprises a seal ring formed over the inactive region of the GaN epi-layer stack and surrounding the lateral GaN transistor, the trench structure being formed between the seal ring and edges of the GaN die, and wherein the conductive metal layer of the trench cladding connects the silicon substrate to a metallization layer of the seal ring.

10. The device structure of claim 6 , wherein the lateral GaN transistor comprises a plurality of transistor islands of a multi-island transistor, and further comprising a plurality of trenches dividing the active device area of the transistor into a plurality of areas, each of said plurality of areas accommodating a plurality of transistor islands.

11. The device structure of claim 6 , wherein the lateral GaN transistor comprises a plurality of transistor islands of a multi-island transistor, and further comprising a plurality of trenches dividing the active device area of the transistor into a plurality of areas, each of said plurality of areas accommodating an individual transistor island.

12. A method of fabrication of a nitride semiconductor device structure as defined in claim 6 , comprising steps of:
providing the silicon substrate having formed thereon a GaN epi-layer structure for a plurality of GaN die, the GaN die being arranged as an array with dicing streets therebetween;
each GaN die comprising:
the GaN epi-layer stack comprising the GaN/AlGaN hetero-layer structure defining the two dimensional electron gas (2DEG) active layer for the lateral GaN transistor;
the source, drain and gate electrodes of the lateral GaN transistor being provided on the front-side of the GaN epi-layer stack over the active area of the GaN die, the inactive area of the GaN epi-layer stack surrounding said active area of each die; and the overlying interconnect structure, comprising the metallization and dielectric layers, defining respective the source, drain and gate connections and contact areas; and

etching the trench structure around all sides of each GaN die, extending through the layers of the overlying interconnect structure, through the layers of the GaN epi-layer stack, and into the surface region of the silicon substrate to the depth below the interface of the GaN epi-layer stack and the silicon substrate, the trench structure being laterally spaced from a dicing street of each edge of the GaN die;
providing the trench cladding comprising the conductive metal layer and the overlying passivation layer the trench cladding extending over the inner sidewalls of the trench structure and sealing the exposed surfaces of the overlying interconnect structure, the layers the GaN epi-layer stack, and the interface of the GaN epi-layer stack and the silicon substrate; and wherein the conductive metal layer of the trench cladding connects the silicon substrate to the source contact area of the lateral GaN transistor.

13. The method of claim 12 , wherein etching the trench structure comprises:
masking at least active areas of each GaN die and part of a surrounding inactive region;
performing a sequence of dry etching steps comprising:
removing layers within the trench extending over the GaN epi-layer stack
removing the layers of the GaN epi-stack within the trench, and
removing the surface region of the silicon substrate within the trench t

Assignees

• Gan Systems Inc

Inventors

• Macelwee Thomas
• Klowak Greg P
• Tweddle Howard

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title