Non-volatile memory device

Patent metadata

Field	Value
Publication number	US-12100452-B2
Application number	US-202217742879-A
Country	US
Kind code	B2
Filing date	May 12, 2022
Priority date	Sep 29, 2021
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A non-volatile memory device is provided. The memory device includes: word lines stacked on a substrate; a string select lines on the word lines, the string select lines being spaced apart from each other in a first horizontal direction and extending in a second horizontal direction; and a memory cell array including memory blocks, each of which includes memory cells connected to the word lines and the string select lines. The string select lines include a first string select line, and a second string select line which is farther from a word line cut region than the first string select line, and a program operation performed on second memory cells connected to a selected word line and the second string select line is performed before a program operation performed on first memory cells connected to the selected word line and the first string select line.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a plurality of word lines stacked in a vertical direction on a substrate;
a plurality of string select lines on the plurality of word lines, the plurality of string select lines being spaced apart from each other in a first horizontal direction and extending in a second horizontal direction, the first and second horizontal directions being parallel with a surface of the substrate, and the second horizontal direction being perpendicular to the first horizontal direction; and
a memory cell array comprising a plurality of memory blocks, each of which comprises a plurality of memory cells connected to the plurality of word lines and the plurality of string select lines,
wherein the plurality of string select lines comprise a first string select line, a second string select line and a third string select line which extend in the first horizontal direction between a first word line cut region and a second word line cut region, and the second string select line is provided between the first string select line and the third string select line, and
wherein a program operation on second memory cells connected to a selected word line and the second string select line is performed before program operations on first memory cells connected to the selected word line and the first string select line and third memory cells connected to the selected word line and the third string select line.

2. The non-volatile memory device of claim 1 , wherein a program order of the plurality of memory cells connected to the selected word line is different from a physical arrangement order of the plurality of string select lines.

3. The non-volatile memory device of claim 1 , wherein channel hole sizes of channel structures corresponding to the first memory cells are substantially equal to channel hole sizes of channel structures corresponding to the second memory cells.

4. The non-volatile memory device of claim 1 , wherein a program speed for the second memory cells is lower than a program speed for the first memory cells.

5. The non-volatile memory device of claim 1 , further comprising a plurality of bit lines on the plurality of string select lines, the plurality of bit lines being spaced apart from each other in the second horizontal direction and extending in the first horizontal direction,
wherein the second memory cells are respectively connected to the plurality of bit lines, and
wherein program operations on the second memory cells are simultaneously performed.

6. The non-volatile memory device of claim 1 , wherein the plurality of word lines comprise a first word line and a second word line which is farther from the substrate than the first word line, and
wherein during program operations on memory cells connected to the first and second word lines, the program operations are sequentially performed on memory cells connected to the second word line and the second string select line, memory cells connected to the second word line and the first string select line, memory cells connected to the first word line and the second string select line, and memory cells connected to the first word line and the first string select line.

7. The non-volatile memory device of claim 1 , wherein the plurality of word lines comprise a first word line and a second word line which is farther from the substrate than the first word line, and
wherein during program operations on memory cells connected to the first and second word lines, the program operations are sequentially performed on memory cells connected to the first word line and the second string select line, memory cells connected to the first word line and the first string select line, memory cells connected to the second word line and the second string select line, and memory cells connected to the second word line and the first string select line.

8. The non-volatile memory device of claim 1 , wherein the plurality of string select lines comprise:
a fourth string select line, a fifth string select line, and a sixth string select line, which extend in the first horizontal direction between the second word line cut region and a third word line cut region, and
wherein, program operations on memory cells connected to the fifth string select line is performed before program operations on memory cells connected to the fourth, and sixth string select lines.

9. The non-volatile memory device of claim 8 , wherein program operations performed on memory cells connected to the first and fourth string select lines are performed before program operations on memory cells connected to the third and sixth string select lines.

10. The non-volatile memory device of claim 8 , wherein a program operation on the second memory cells connected to the selected word line and the second string select line is performed before a program operation on memory cells connected to the selected word line and the fifth string select line.

11. The non-volatile memory device of claim 1 , wherein the plurality of string select lines comprise:
the first string select line, the second string select line, the third string select line, and a fourth string select line, which extend in the first horizontal direction between the first word line cut region and the second word line cut region; and
a fifth string select line, a sixth string select line, a seventh string select line, and an eighth string select line, which extend in the first horizontal direction between the second word line cut region and a third word line cut region, and
wherein program operations on memory cells connected to the second, fourth, sixth, and seventh string select lines are performed before program operations on memory cells connected to the first, third, fifth, and eighth string select lines.

12. The non-volatile memory device of claim 11 , wherein a program operation on memory cells connected to the first string select line is performed before a program operation on memory cells connected to the fifth and eighth string select lines.

13. The non-volatile memory device of claim 11 , wherein a program operation on the second memory cells connected to the selected word line and the second string select line is performed before a program operation on memory cells connected to the selected word line and the sixth string select line.

14. The non-volatile memory device of claim 1 , wherein the plurality of word lines, the plurality of string select lines, and the memory cell array are arranged in a memory cell region,
wherein the memory cell array further comprises a first metal pad,
wherein the non-volatile memory device further comprises a peripheral circuit region, which comprises a second metal pad which extends in the vertical direction and is connected to the memory cell region via the first metal pad and the second metal pad, and
wherein the first metal pad and the second metal pad are connected to each other in a bonding manner.

15. A non-volatile memory device comprising:
a memory cell array comprising a plurality of memory blocks, each of which comprises a plurality of memory cells;
a row decoder connected to the memory cell array via a plurality of word lines and a plurality of string select lines, the plurality of word lines being stacked in a vertical direction on a substrate, and the plurality of string select lines extending in a horizontal direction on the plurality of word lines; and
a control logic circuit configured to, according to a program command and an address, generate a row address based on the address such that the plurality of memory cells are programmed in an order

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Kuihan
• Park Sangwon
• Kim Minyong
• Choi Jekyung
• Choi Junho

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title