Memory device having only the top poly cut

Patent metadata

Field	Value
Publication number	US-2016372198-A1
Application number	US-201514742944-A
Country	US
Kind code	A1
Filing date	Jun 18, 2015
Priority date	Jun 18, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n−1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.

First claim

1 . A structure of a memory device, the structure of the memory device comprising:
a substrate; and a 3D array of nonvolatile memory cells, the 3D array including:
a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers,
wherein the top layer further comprises n−1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer thus not extending into the bottom layers.

2 . The structure of the memory device of claim 1 , further comprising:
a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.

3 . The structure of the memory device of claim 1 , further comprising:
a control circuit configured to decode bit lines utilizing the SSLs.

4 . The structure of the memory device of claim 1 , further comprising:
a common select line (CSL) on each side of the bit lines, wherein the CSL is formed with any one of poly-silicon, Epi, or metal.

5 . The structure of the memory device according to claim 1 , wherein the memory device is one of a non-volatile memory device, an embedded memory device, a floating gate memory device, or a charge trapping memory device.

6 . The structure of the memory device according to claim 1 , wherein the substrate is one of an n-type, un-doped, a p-type, or a triple well structure including n-well, p-well, and deep N-well.

7 . The structure of the memory device according to claim 1 , wherein the ONO stack could be any one of an insulator/trapping or trapping/insulator combination and the channel is filled with any one of a poly only or poly/insulator combination.

8 . The structure of the memory device according to claim 1 , wherein the apparatus may be utilized to control a ROM or NAND memory device.

9 . The structure of the memory device of claim 1 , wherein the memory device is a non-volatile memory device comprises a flash memory.

10 . The structure of the memory device of claim 1 , wherein the memory device is a non-volatile memory device comprises a NAND flash memory.

11 . A non-volatile memory device comprising:
a substrate; and 3D array of nonvolatile memory cells, the 3D array including:
a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers,
wherein the top layer further comprises n−1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer thus not extending into the bottom layers.

12 . The non-volatile memory device of claim 11 , further comprising:
a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.

13 . The non-volatile memory device of claim 11 , further comprising:
a control circuit configured to decode bit lines utilizing the SSLs.

14 . The non-volatile memory device of claim 11 , further comprising:
a common select line (CSL) on each side of the bit lines, wherein the CSL is formed with any one of poly-silicon, Epi, or metal.

15 . The non-volatile memory device according to claim 11 , wherein the substrate is one of an n-type, un-doped, a p-type, or a triple well structure including n-well, p-well, and deep N-well.

16 . The non-volatile memory device according to claim 11 , wherein the ONO stack could be any one of an insulator/trapping or trapping/insulator combination and the channel is filled with any one of a poly only or poly/insulator combination.

17 . The non-volatile memory device according to claim 11 , wherein the non-volatile memory device comprising a flash memory.

18 . The non-volatile memory device according to claim 11 , wherein the non-volatile memory device comprising a NAND flash memory.

19 . A method of manufacturing a semiconductor device comprising:
providing a substrate; forming a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, etching the top layer to comprise n−1 cuts, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers; and filling the n−1 cuts with insulating material, wherein the etching and filling each cut forms the SSLs along the top layer.

20 . The method according to claim 19 , further comprising:
providing a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.

21 . The method according to claim 19 , further comprising:
decoding one or more bit lines utilizing the SSLs.

22 . The method according to claim 19 , wherein the semiconductor device is one of a non-volatile memory device, an embedded memory device, a floating gate memory device, or a charge trapping memory device.

23 . The method according to claim 19 , wherein the substrate is one of an n-type, un-doped, a p-type, or a triple well structure including n-well, p-well, and deep N-well.

Assignees

• Macronix Int Co Ltd

Inventors

• Lee Chih-Wei
• Ku Shaw-Hung
• Cheng Cheng-Hsien

Classifications

• H01L21/76802

  Electricity · mapped topic

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11551

  Electricity · mapped topic

• H01L27/11578

  Electricity · mapped topic

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title