Grouping memory cells into sub-blocks for program speed uniformity

Patent metadata

Field	Value
Publication number	US-9959932-B1
Application number	US-201715437718-A
Country	US
Kind code	B1
Filing date	Feb 21, 2017
Priority date	Feb 21, 2017
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of word line layers which are vertically spaced apart from one another by dielectric layers;
a set of NAND strings extending through the plurality of word line layers, the set of NAND strings comprises NAND strings in an interior sub-block of a block region, NAND strings in a first edge portion of the block region and NAND strings in a second edge portion of the block region, wherein the interior sub-block is between the first and second edge portions;
a first set of bit lines connected to the NAND strings of the first edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the second edge portion; and
a second set of bit lines connected to the NAND strings of the second edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the first edge portion, wherein a thickness of a block oxide layer in the NAND strings of the first and second edge portions is less than a thickness of a block oxide layer in the NAND strings of the interior sub-block.

2. The memory device of claim 1 , further comprising:
a first edge select gate layer connected to select gate transistors of the NAND strings of the first edge portion;
a second edge select gate layer connected to select gate transistors of the NAND strings of the second edge portion;
a conductive path connecting the first and second edge gate layers; and
an interior select gate layer which is between the first and second edge select gate layers and is connected to select gate transistors of the NAND strings of the interior sub-block.

3. The memory device of claim 2 , wherein:
the first and second edge select gate layers are not connected to the interior select gate layer.

4. The memory device of claim 1 , wherein:
the plurality of word line layers have opposing first and second edges; and
the NAND strings of the first and second edge portions are adjacent to the first and second edges, respectively.

5. The memory device of claim 4 , further comprising:
first and second isolation areas adjacent to the first and second edges, respectively, and extending from a bottom of the plurality of word line layers to a top of the plurality of word line layers.

6. The memory device of claim 4 , further comprising:
first and second metal interconnects adjacent to the first and second edges, respectively, and extending from a bottom of the plurality of word line layers to a top of the plurality of word line layers, wherein a metal of the metal interconnect and a metal of the plurality of word line layers comprise tungsten.

7. The memory device of claim 1 , wherein:
the set of NAND strings is arranged in rows; and
a number of rows of the NAND strings in the first and second edge portions together is equal to a number of rows of the NAND strings in the interior sub-block.

8. The memory device of claim 1 , wherein:
the set of NAND strings is arranged in rows; and
a number of rows of the NAND strings in the first and second edge portions together is less than a number of remaining rows of the NAND strings in the block region.

9. The memory device of claim 1 , wherein:
the set of NAND strings extends vertically through the plurality of word line layers.

10. The memory device of claim 1 , wherein:
the set of NAND strings is arranged in rows; and
a number of rows of the NAND strings in the first and second edge portions together is less than a number of rows of the NAND strings in the interior sub-block.

11. The memory device of claim 1 , wherein:
the first edge portion is at one edge of the block region and the second edge portion is at an opposite edge of the block region.

12. The memory device of claim 1 , wherein:
the first edge portion is adjacent to a local interconnect or isolation region at one edge of the block region; and
the second edge portion is adjacent to a local interconnect or isolation region at another edge of the block region which is opposite the one edge.

13. The memory device of claim 1 , wherein:
in a direction in which the first and second sets of bit lines extend, a width of the first edge portion is equal to a width of the second edge portion and less than a width of the interior sub-block.

14. The memory device of claim 1 , wherein:
in a direction in which the first and second sets of bit lines extend, widths of the first and second edge portions are less than a width of the interior sub-block.

15. The memory device of claim 1 , wherein:
the first and second edge portions are adjacent to the interior sub-block.

16. The memory device of claim 1 , wherein:
the interior sub-block is undivided.

Assignees

• Sandisk Technologies Llc

Inventors

• Zhang Zhengyi
• Dong Yingda
• Kai James
• Alsmeier Johann

Classifications

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title