Non-volatile memory devices and methods of programming the same

Patent metadata

Field	Value
Publication number	US-10325657-B2
Application number	US-201715793221-A
Country	US
Kind code	B2
Filing date	Oct 25, 2017
Priority date	Jan 25, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Methods of programming a non-volatile memory device including N string selection lines, a word line, first and second bit line groups are provided. The method may include sequentially programming first memory cells that are connected to the word line and at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied first to N-th addresses, and then sequentially programming second memory cells that are connected to the word line and at least one bit line included in the second bit line group by sequentially selecting one of the N string selection lines in response to sequentially applied N+1-th to 2N-th addresses.

First claim

What is claimed is:

1. A method of programming a non-volatile memory device comprising N string selection lines, a word line, a first bit line group and a second bit line group, the method comprising:
sequentially programming first memory cells that are connected to the word line and at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied first to N-th addresses; and then
sequentially programming second memory cells that are connected to the word line and at least one bit line included in the second bit line group by sequentially selecting one of the N string selection lines in response to sequentially applied N+1-th to 2N-th addresses,
wherein N is a natural number greater than or equal to 2.

2. The method of claim 1 , wherein the first bit line group comprises a plurality of first bit lines, and
wherein third memory cells that are connected to the word line, an M-th string selection line and any one of the plurality of first bit lines are simultaneously programmed.

3. The method of claim 1 , wherein a memory cell of the first memory cells that is connected to an M-th string selection line is programmed before a memory cell of the second memory cells that is connected to the M-th string selection line.

4. The method of claim 1 , wherein the N string selection lines comprise a first string selection line and a second string selection line,
wherein sequential programming the first memory cells comprises:
receiving the first address and a first program command;
programming at least one memory cell that is connected to the word line, the at least one bit line included in the first bit line group, and the first string selection line, in response to the first address and the first program command;
receiving a second address and a second program command; and
programming at least one memory cell that that is connected to the word line, the at least one bit line included in the first bit line group, and the second string selection line, in response to the second address and the second program command.

5. The method of claim 4 , wherein sequential programming the second memory cells comprises:
receiving a third address and a third program command;
programming at least one memory cell that is connected to the word line, the at least one bit line included in the second bit line group, and the first string selection line, in response to the third address and the third program command;
receiving a fourth address and a fourth program command; and
programming at least one memory cell that is connected to the word line, the at least one bit line included in the second bit line group, and the second string selection line, in response to the fourth address and the fourth program command.

6. The method of claim 4 , further comprising:
converting the first address into a first corrected address after receiving the first address and the first program command; and
converting the second address into a second corrected address after receiving the second address and the second program command,
wherein programming the at least one memory cell in response to the first address and the first program command comprises programming the at least one memory cell in response to the first corrected address, and
wherein programming the at least one memory cell in response to the second address and the second program command comprises programming the at least one memory cell in response to the second corrected address.

7. The method of claim 6 , wherein converting the first address into the first corrected address and converting the second address into the second corrected address comprise placing a string selection line address at a lower bit than a bit line group address.

8. The method of claim 6 , wherein the first address comprises a logical address, and
wherein the first corrected address comprises a word line address, a bit line group address, and a string selection line address.

9. The method of claim 1 , after sequential programming the second memory cells, further comprising:
sequentially programming third memory cells that are connected to an adjacent word line adjacent to the word line and the at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied 2N+1-th to 3N-th addresses; and then
sequentially programming fourth memory cells connected to the adjacent word line and the at least one bit line included in the second bit line group by sequentially selecting the N string selection lines in response to sequentially applied 3N+1-th to 4N-th addresses.

10. The method of claim 1 , wherein the memory cells are multi-level cells (MLCs),
wherein sequential programming the first memory cells comprises sequentially performing least significant bit (LSB) program operations on the first memory cells, and
wherein sequential programming the second memory cells comprises sequentially performing LSB program operations on the second memory cells.

11. The method of claim 10 further comprising, after sequential programming the second memory cells, sequentially performing following operations:
sequentially performing LSB program operations on third memory cells that are connected to an adjacent word line adjacent to the word line and the at least one bit line included in the first bit line group by sequentially selecting the N string selection lines;
sequentially performing LSB program operations on fourth memory cells that are connected to the adjacent word line and the at least one bit line included in the second bit line group by sequentially selecting the N string selection lines;
sequentially performing most significant bit (MSB) program operations on the first memory cells by sequentially selecting the N string selection lines;
sequentially performing MSB program operations on the second memory cells by sequentially selecting the N string selection lines;
sequentially performing MSB program operations on the third memory cells by sequentially selecting the N string selection lines; and
sequentially performing MSB program operations on the fourth memory cells by sequentially selecting the N string selection lines.

12. The method of claim 1 , wherein the non-volatile memory device comprises a vertical NAND flash memory comprising a plurality of bit lines, and
wherein K bit lines of the plurality of bit lines are connected to one page buffer, and K is equal to a number of bit line groups.

13. The method of claim 1 , wherein the non-volatile memory device is a planar NAND flash memory comprising a plurality of bit lines, and
wherein K bit lines of the plurality of bit lines are connected to one page buffer, and K is equal to a number of bit line groups.

14. The method of claim 1 , wherein the non-volatile memory device comprises a plurality of bit lines and four bit line groups, and
wherein four bit lines of the plurality of bit lines are connected to one page buffer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shim Dong-Kyo
• Park Sang-Won
• Jeon Su-Chang

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title