Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12096616-B2
Application number	US-202117389752-A
Country	US
Kind code	B2
Filing date	Jul 30, 2021
Priority date	Sep 18, 2020
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

An embodiment of the disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, a bit line structure located on the substrate, a capacitor contact hole located on two opposite sides of the bit line structure, and an isolation sidewall. The isolation sidewall is located between the bit line structure and the capacitor contact hole. A gap is provided between the isolation sidewalls located on the two opposite sides of the bit line structure. The gap is located on the bit line structure.

First claim

The invention claimed is:

1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate, and sequentially stacking a bit line structure and a first sacrificial layer on the substrate, wherein capacitor contact holes are located on two opposite sides of the bit line structure, and the first sacrificial layer is located on the bit line structure;
forming an isolation sidewall covering a sidewall of the bit line structure and a sidewall of the first sacrificial layer; and
removing the first sacrificial layer to form a gap, wherein the gap is located on the bit line structure.

2. The manufacturing method of a semiconductor structure of claim 1 , wherein a top surface of the first sacrificial layer is covered with a top isolation layer;
wherein forming the gap comprises:
filling a second sacrificial layer between the adjacent bit line structures;
forming a first mask layer; and
removing a part of the first sacrificial layer, a part of the top isolation layer, a part of the isolation sidewall and a part of the second sacrificial layer through the first mask layer in a same etching process to form a first gap.

3. The manufacturing method of a semiconductor structure of claim 2 , after forming the first gap, wherein the method further comprises:
forming an isolation layer located between the adjacent bit line structures and a first sealing layer for sealing a top opening of the first gap in a same deposition process.

4. The manufacturing method of a semiconductor structure of claim 3 , after forming the isolation layer and the first sealing layer, wherein the method further comprises:
removing a remaining part of the second sacrificial layer to form the capacitor contact holes; and
filling the capacitor contact holes to form a capacitor contact window.

5. The manufacturing method of a semiconductor structure of claim 3 , after forming the isolation layer and the first sealing layer, wherein the method further comprises:
removing a remaining part of the first sacrificial layer to form a second gap;
forming the gap by the first gap and the second gap;
forming a second sealing layer for sealing a top opening of the second gap; and
forming a sealing layer by the first sealing layer and the second sealing layer.

6. The manufacturing method of a semiconductor structure of claim 5 , wherein removing the remaining part of the first sacrificial layer comprises:
removing a remaining part of the top isolation layer by adopting a planarization process to expose the remaining part of the first sacrificial layer.

Assignees

• Changxin Memory Tech Inc

Inventors

• Cheng Ming
• Jin Xing
• Li Ran

Classifications

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/482 Primary

  Bit lines · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title