Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9331072-B2
Application number	US-201414165721-A
Country	US
Kind code	B2
Filing date	Jan 28, 2014
Priority date	Jan 28, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a pair of spacers spaced apart from, each other on a substrate, wherein the pair of spacers define a recess;
a lower conductive pattern in the recess on the substrate;
an upper conductive pattern in the recess on the lower conductive pattern, wherein the upper conductive pattern exposes a portion of an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern, an inner sidewall of one of the pair of spacers, the portion of the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern define a space, and the upper conductive pattern has an etch selectivity with respect to the lower conductive pattern; and
a capping pattern on the upper conductive pattern, wherein the capping pattern seals a top portion of the space such that a cavity is disposed under the capping pattern,
wherein the lower and upper conductive patterns comprise a gate electrode.

2. The integrated circuit device of claim 1 , wherein an uppermost surface of the upper conductive pattern is lower than uppermost surfaces of the pair of spacers relative to an upper surface of the substrate.

3. The integrated circuit device of claim 2 , wherein the capping pattern is in the recess.

4. The integrated circuit device of claim 1 , wherein the cavity comprises an air-gap.

5. The integrated circuit device of claim 1 , further comprising an insulating pattern in the cavity.

6. The integrated circuit device of claim 5 , wherein the insulating pattern comprises SiCN, SiBCN or SiOCN.

7. The integrated circuit device of claim 1 , further comprising
a gate insulator between the substrate and the gate electrode, wherein the gate insulator extends between the inner sidewall of the one of the pair of spacers and a sidewall of the gate electrode.

8. The integrated circuit device of claim 7 , wherein an uppermost surface of the lower conductive pattern and an uppermost surface of the gate insulator are at an equal level.

9. The integrated circuit device of claim 7 , farther comprising a work function control pattern between the substrate and the lower conductive pattern.

10. The integrated circuit device of claim 9 , wherein an upper surface of the work function control pattern comprises a recess.

11. The integrated circuit device of claim 9 , wherein the lower conductive pattern covers an entire upper surface of the work function control pattern.

12. The integrated circuit device of claim 9 , wherein the work function control pattern conformally extends on a portion of a sidewall and a bottom surface of the upper conductive pattern, and the lower conductive pattern conformally extends between the upper conductive pattern and the work function control pattern.

13. The integrated circuit device of claim 1 , wherein the lower conductive pattern partially surrounds the sidewall of the upper conductive pattern.

14. The integrated circuit device of claim 1 , further comprising:
a conductive region on the substrate adjacent the one of the pair of spacers and out of the recess;
an insulating layer on the capping pattern, the pair of spacers and the conductive region; and
a conductive pattern passing through the insulating layer, wherein the conductive pattern contacts the one of the pair of spacers and the conductive region.

15. The integrated circuit device of claim 14 , wherein the insulating layer has an etch selectivity with respect to the pair of spacers.

16. The integrated circuit device of claim 14 , wherein the conductive pattern contacts an upper surface of the capping pattern, and the insulating layer has an etch selectivity with respect to the capping pattern.

17. The integrated circuit device of claim 1 , wherein;
the pair of spacers comprise a first pair of spacers, the recess comprises a first recess, the lower and upper conductive patterns comprise a first gate electrode, and the capping pattern comprises a first capping pattern;
the first pair of spacers, the first gate electrode, and the first capping pattern comprise a first gate structure in a first region of the substrate; and
the device further comprises a second gate structure in a second region of the substrate, wherein the second gate structure is free of a cavity and comprises:
a second pair of spacers spaced apart from each other on the substrate, wherein the second pair of spacers defines a second recess;
a second gate electrode in the second recess on the substrate, wherein the second gate electrode comprises a material included in the lower conductive pattern of the first gate electrode; and
a second capping pattern on the second gate electrode.

18. The integrated circuit device of claim 17 , wherein art upper surface of the second gate electrode is planar and the second capping pattern contacts the upper surface of the second gate electrode.

19. The integrated circuit device of claim 17 , wherein:
the material included in the lower conductive pattern comprises a first material and the upper conductive pattern of the first gate electrode comprises a second material; and
the second material is absent from the second gate electrode pattern.

20. An integrated circuit device, comprising:
a pair of spacers spaced apart from each other on a substrate, wherein the pair of spacers define a recess;
a conductive pattern in the recess on the substrate, wherein the conductive pattern comprises an upper portion and a lower portion, and a width of the upper portion is smaller than a width of the lower portion such that a space is defined by a sidewall of the upper portion of the conductive pattern and an inner sidewall of one of the pair of spacers, and wherein the conductive pattern comprises a gate electrode; and
a capping pattern in the recess on the conductive pattern, wherein the capping pattern seals a top portion of the space such that a cavity is disposed under the capping pattern.

21. The integrated circuit device of claim 20 , wherein the upper portion of the conductive pattern has an etching selectivity with respect to the lower portion of the conductive pattern.

22. The integrated circuit device of claim 20 , wherein an uppermost surface of the conductive pattern is lower than uppermost surfaces of the pair of spacers relative to an upper surface of the substrate.

23. An integrated circuit device, comprising:
a conductive pattern on a substrate, wherein the conductive pattern comprises an upper conductive pattern and a lower conductive pattern, wherein the lower conductive pattern has an etch selectivity with respect to the upper conductive pattern and extends between the upper conductive pattern and the substrate, and wherein the conductive pattern comprises a gate electrode;
a spacer on the substrate adjacent a sidewall of the conductive pattern;
a cavity between a sidewall of the upper conductive pattern and an inner sidewall of the spacer; and
a capping pattern on the conductive pattern and on the spacer.

24. The integrated circuit device of claim 23 , wherein the capping pattern contacts the inner sidewall of the spacer.

25. The integrated circuit device of claim 23 , wherein an uppermost surface of the upper conductive pattern is higher than an uppermost surface of the lower conductive pattern relative to an upper surface of the substrate.

26. The integrated circuit device of claim 25 , wherein the upper conduc

Assignees

• Seo Kang-Ill
• Lee Jin-Wook
• Samsung Electronics Co Ltd

Inventors

• Seo Kang-Ill
• Lee Jin-Wook

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D84/0147 Primary

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title