Semiconductor device with air gap and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9337202-B2
Application number	US-201514857550-A
Country	US
Kind code	B2
Filing date	Sep 17, 2015
Priority date	Apr 8, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is to formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device comprising:
forming a dielectric layer over a substrate;
forming an opening by etching the dielectric layer;
forming a first conductive pattern in the opening;
forming sacrificial spacer on sidewalls of the opening over the first conductive pattern;
forming an ohmic contact layer over the first conductive pattern;
forming a second conductive pattern over the ohmic contact layer;
forming air gap by removing the sacrificial spacer; and
forming a third conductive pattern over the second conductive pattern to cap the air gap.

2. The method of claim 1 , wherein the forming of the third conductive pattern includes:
forming a barrier layer over an entire surface including the second conductive pattern and the air gap;
forming a conductive layer over the barrier layer to fill the opening; and
planarizing the conductive layer and the barrier layer.

3. The method of claim 2 , wherein of the barrier layer and the conductive layer include a metal-containing material, respectively.

4. The method of claim 1 , further comprising:
after the forming of the sacrificial spacer, recessing a surface of the first conductive pattern.

5. The method of claim 1 , wherein the first conductive pattern include a silicon-containing material.

6. The method of claim 1 , wherein the second conductive pattern and the third conductive pattern include a metal-containing material respectively.

7. The method of claim 1 , wherein the ohmic contact layer includes cobalt silicide with a phase of CoSi 2 .

8. A method for fabricating a semiconductor device comprising:
forming a plurality of conductive structures which include first conductive patterns, over a substrate;
forming a dielectric layer over the conductive structures;
forming openings between the conductive structures by etching the dielectric layer;
forming second conductive patterns which are recessed to be lower than the first conductive patterns, in the openings;
forming sacrificial spacers on sidewalk of the openings over the second conductive patterns;
forming an ohmic contact layer over the second conductive patterns;
forming third conductive patterns over the ohmic contact layer, defining air gaps by removing the sacrificial spacers; and
forming fourth conductive patterns over the third conductive patterns, to cap the air gaps.

9. The method of claim 8 , further comprising:
after the forming of the sacrificial spacers, recessing surfaces of the second conductive patterns in a manner self-aligned with the sacrificial spacers.

10. The method of 8 , wherein the first conductive patterns include bit lines.

11. The method of claim 8 , wherein stack structures of the second conductive patterns, the ohmic contact layer, the third conductive patterns and the fourth conductive patterns include storage node contact plugs.

12. The method of claim 8 , wherein the second conductive patterns include a silicon-containing material, and the third conductive patterns include a metal-containing material.

13. The method of claim 8 , wherein the ohmic contact layer includes cobalt silicide with a phase of CoSi 2 .

14. The method of claim 8 , wherein the forming of the fourth conductive patterns comprising:
forming a barrier layer to cap the third conductive patterns and the air gaps;
forming a metal-containing layer over the barrier layer to ill the openings; and
planarizing the metal-containing layer and the barrier layer.

15. The method of claim 14 , wherein the barrier layer includes a titanium-containing material.

16. The method of claim 8 , further comprising:
before the forming of the conductive structures, forming buried gate type transistors which include gate electrodes buried in the substrate.

17. The method of claim 8 , further comprising:
after the forming of the fourth conductive pattern forming capacitors over the fourth conductive patterns.

Assignees

• Sk Hynix Inc

Inventors

• Lim Sung-Won
• Yeom Seung-Jin
• Lee Hyo-Seok

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title