Semiconductor device with damascene bit line and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2016133564-A1
Application number	US-201614988238-A
Country	US
Kind code	A1
Filing date	Jan 5, 2016
Priority date	Oct 12, 2011
Publication date	May 12, 2016
Grant date	—

Abstract

A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (SNC) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate having a plurality of contact surfaces; an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces; a storage node contact (SNC) plug filling the first open portion; and a damascene structure filing the second open portion and comprising a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap that is formed between the bit line and the spacer, wherein the bit line comprises a conductive material which has a volume contraction property at a certain temperature.

2 . The semiconductor device of claim 2 , wherein the storage node contact (SNC) plug comprises a conductive material which has not volume contraction property at the certain temperature.

3 . A semiconductor device comprising:
a substrate having a plurality of contact surfaces; an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which has a line shape to expose the other contact surfaces and a first portion between two adjacent contact surfaces among the other contact surfaces; a storage node contact (SNC) plug filling the first open portion; and a damascene structure filing the second open portion and comprising a bit line, a spacer formed on at least both sidewalls of the bit line, and an air gap that is formed between the bit line and the spacer, wherein uppermost portions of the other contact surfaces include a metal silicide, the spacer is further formed under the bit line and the air gap in a region overlapping with the first portion, and a bottom surface of the bit line directly contacts the metal silicide while directly contacting the spacer in the region overlapping with the first portion, wherein the air gap surrounds the bit line in the region overlapping with the first portion.

4 . The semiconductor device of claim 3 wherein the damascene structure further comprises a capping layer formed over the bit line, the spacer, and the air gap.

5 . The semiconductor device of claim 3 , wherein the air gap is further formed at the entire interface between the capping layer and the bit line.

Assignees

• Sk Hynix Inc

Inventors

• Lee Nam-Yeal

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title