Enhancement-mode semiconductor device and preparation method therefor

Patent metadata

Field	Value
Publication number	US-12094962-B2
Application number	US-202117356541-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Jan 15, 2019
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

The present invention relates to an enhancement-mode semiconductor device and a preparation method therefor. The device includes a substrate, a semiconductor epitaxial layer, a gate electrode, a source electrode, and a drain electrode. The epitaxial layer includes a nitride nucleation layer, a nitride stress buffer layer, a nitride channel layer, a primary epitaxial nitride barrier layer, a p-type nitride layer and a secondary epitaxial nitride barrier layer. By means of etching, the p-type nitride in a gate electrode region is reserved, realizing the depletion of a gate electrode channel. By means of maskless regrowth, the secondary epitaxial nitride barrier layer is grown on the primary epitaxial barrier layer and the p-type nitride layer in the gate electrode region, realizing a high-conduction access region.

First claim

What is claimed is:

1. An enhancement-mode semiconductor device, comprising a substrate, a semiconductor epitaxial layer grown on the substrate, a gate electrode, a source electrode and a drain electrode, wherein the epitaxial layer comprises a nitride nucleation layer, a nitride stress buffer layer, a nitride channel layer, a primary epitaxial nitride barrier layer, a p-type nitride layer and a secondary epitaxial nitride barrier layer from bottom to top; the p-type nitride layer is only reserved on the primary epitaxial nitride barrier layer in a gate electrode region, realizing the depletion of a two-dimensional electron gas channel under the gate electrode; a regrowth process of the secondary epitaxial nitride barrier layer is maskless; the secondary epitaxial nitride barrier layer is located on the primary epitaxial nitride barrier layer and the p-type nitride layer in the gate electrode region; and gate electrode metal is in direct contact with the secondary epitaxial nitride barrier layer,
wherein the primary epitaxial nitride barrier layer is a material of one of AlGaN, AlInN, InGaN, AlInGaN and AlN or a material of a combination of any of AlGaN, AlInN, InGaN, AlInGaN and AlN, an Al component content in the primary epitaxial nitride barrier layer is 1% to 30%, and a thickness of the primary epitaxial nitride barrier layer is 1 nm to 30 nm; the secondary epitaxial nitride barrier layer is one of AlGaN, AlInN, InGaN, AlInGaN and AlN or a combination of any of AlGaN, AlInN, InGaN, AlInGaN and AlN, an Al component content in the secondary epitaxial nitride barrier layer is 1% to 40%, and a thickness of the secondary epitaxial nitride barrier layer is 1 nm to 40 nm; the p-type nitride layer is GaN, AlGaN, AlInN or AlInGaN, and a thickness of the p-type nitride layer is not less than 5 nm,
wherein an AlN space layer is further inserted between the primary epitaxial nitride barrier layer and the nitride channel layer, and a thickness of the AlN space layer is 0.3 nm to 3 nm.

2. The enhancement-mode semiconductor device according to claim 1 , wherein the substrate is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate, a free-standing GaN substrate or AlN; the nitride stress buffer layer contains any one of AlN, AlGaN, GaN and SiN or a combination of AlN, AlGaN, GaN and SiN; the nitride nucleation layer is an Al-containing nitride layer; and the nitride channel layer is a GaN or AlGaN layer.

3. The enhancement-mode semiconductor device according to claim 2 , wherein the p-type nitride layer in the gate electrode region is reserved, and the primary epitaxial nitride barrier layer beyond the p-type nitride layer in the gate electrode region is partially removed, and a thickness of the rest primary epitaxial nitride barrier layer is 1 nm to 30 nm.

4. The enhancement-mode semiconductor device according to claim 3 , wherein a cap layer or passivation layer is in-situ grown on the secondary epitaxial nitride barrier layer; the cap layer is GaN, and a thickness of the cap layer is 0.5 nm to 8 nm; and the passivation layer is SiN x , SiO 2 , Al 2 O 3 , AlO x N y , GaO x , GaO x N y , and a thickness of the passivation layer is 1 nm to 100 nm.

5. The enhancement-mode semiconductor device according to claim 4 , wherein the source electrode and the drain electrode are in ohmic contact, and the gate electrode is in ohmic contact or Schottky contact.

6. The enhancement-mode semiconductor device according to claim 1 , wherein an AlN blocking layer is further inserted between the p-type nitride layer and the primary epitaxial nitride barrier layer, and a thickness of the AlN blocking layer is 0.3 nm to 5 nm.

7. The enhancement-mode semiconductor device according to claim 6 , wherein the p-type nitride layer in the gate electrode region is reserved, and the primary epitaxial nitride barrier layer beyond the p-type nitride layer in the gate electrode region is partially removed, and a thickness of the rest primary epitaxial nitride barrier layer is 1 nm to 30 nm.

8. The enhancement-mode semiconductor device according to claim 1 , wherein the Al component content in the secondary epitaxial nitride barrier layer is higher than that in the primary epitaxial nitride barrier layer.

9. The enhancement-mode semiconductor device according to claim 8 , wherein the p-type nitride layer in the gate electrode region is reserved, and the primary epitaxial nitride barrier layer beyond the p-type nitride layer in the gate electrode region is partially removed, and a thickness of the rest primary epitaxial nitride barrier layer is 1 nm to 30 nm.

10. The enhancement-mode semiconductor device according to claim 1 , wherein the p-type nitride layer in the gate electrode region is reserved, and the primary epitaxial nitride barrier layer beyond the p-type nitride layer in the gate electrode region is partially removed, and a thickness of the rest primary epitaxial nitride barrier layer is 1 nm to 30 nm.

11. A preparation method for an enhancement-mode semiconductor device, comprising the following steps:
S 1 growing a nitride nucleation layer on a substrate;
S 2 growing a nitride stress buffer layer on the nitride nucleation layer;
S 3 growing a nitride channel layer on the nitride stress buffer layer;
S 4 growing a primary epitaxial nitride barrier layer on the nitride channel layer;
S 5 growing a p-type nitride layer on the primary epitaxial nitride barrier layer;
S 6 forming a p-type nitride layer which is only reserved on the primary epitaxial nitride barrier layer in a gate electrode region, by photolithography patterning and etching methods;
S 7 growing a secondary epitaxial nitride barrier layer; wherein the secondary epitaxial nitride barrier layer is located on the primary epitaxial barrier layer and the p-type nitride layer, and a growth process of the secondary epitaxial nitride barrier layer is maskless;
S 8 activating acceptor doping elements in the p-type nitride layer through high-temperature annealing;
S 9 performing dry etching to complete device isolation, and simultaneously etching out contact regions of source electrode and drain electrode;
S 10 forming source electrode and drain electrode ohmic contact metal on source electrode and drain electrode regions; and
S 11 forming gate electrode metal on the p-type nitride layer and secondary epitaxial nitride barrier layer in a gate electrode region; wherein gate electrode metal is in direct contact with the secondary epitaxial nitride barrier layer,
wherein the primary epitaxial nitride barrier layer is a material of one of AlGaN, AlInN, InGaN, AlInGaN and AlN or a material of a combination of any of AlGaN, AlInN, InGaN, AlInGaN and AlN, an Al component content in the primary epitaxial nitride barrier layer is 1% to 30%, and a thickness of the primary epitaxial nitride barrier layer is 1 nm to 30 nm; the secondary epitaxial nitride barrier layer is one of AlGaN, AlInN, InGaN, AlInGaN and AlN or a combination of any of AlGaN, AlInN, InGaN, AlInGaN and AlN, an Al component content in the secondary epitaxial nitride barrier layer is 1% to 40%, and a thickness of the secondary epitaxial nitride barrier layer is 1 nm to 40 nm; the p-type nitride layer is GaN, AlGaN, AlInN or AlInGaN, and a thickness of the p-type nitride layer is not less than 5 nm,
wherein an AlN space layer is further inserted between the primary epitaxial nitride barrier layer and the nitride channel layer, and a thickness of the AlN space layer is 0.3 nm to 3 nm.

Assignees

• Univ Sun Yat Sen

Inventors

• Liu Yang
• He Liang

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/411

  for FETs · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title