Semiconductor devices and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-11335797-B2
Application number	US-201916387063-A
Country	US
Kind code	B2
Filing date	Apr 17, 2019
Priority date	Apr 17, 2019
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

A semiconductor device is provided. The semiconductor device includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, and a nitride layer disposed on the barrier layer. The semiconductor device also includes a compound semiconductor layer that includes an upper portion and a lower portion, wherein the lower portion penetrates through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of the barrier layer and extending onto the nitride layer. The semiconductor device further includes a gate electrode disposed on the compound semiconductor layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a channel layer disposed on a substrate;
a barrier layer disposed on the channel layer;
a nitride layer disposed on the barrier layer;
a compound semiconductor layer comprising an upper portion and a lower portion, wherein the lower portion penetrates physically through the nitride layer and a portion of the barrier layer;
a spacer layer conformally disposed on a portion of the barrier layer and extending onto the nitride layer, wherein the spacer continuously extends between a bottom surface of the compound semiconductor layer and the barrier, and the spacer is in contact with a top surface of the barrier layer;
a gate electrode disposed on the compound semiconductor layer; and
a pair of source/drain electrodes disposed on opposite sides of the gate electrode, wherein the pair of source/drain electrodes extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.

2. The semiconductor device of claim 1 , wherein the nitride layer comprises gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN), or a combination thereof.

3. The semiconductor device of claim 1 , wherein a thickness of the nitride layer ranges from about 1 nm to about 20 nm.

4. The semiconductor device of claim 1 , wherein a bandgap of the nitride layer is larger than a bandgap of the compound semiconductor layer and a bandgap of the spacer layer.

5. The semiconductor device of claim 4 , wherein the spacer layer comprises aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlGaInN), or a combination thereof.

6. The semiconductor device of claim 1 , wherein a thickness of the spacer layer ranges from about 1 nm to about 7 nm.

7. The semiconductor device of claim 1 , wherein the pair of source/drain electrodes penetrates through the barrier layer and extends to the channel layer.

8. The semiconductor device of claim 1 , wherein the barrier layer has a maximum thickness, wherein the maximum thickness ranges from about 10 nm to about 60 nm.

9. The semiconductor device of claim 8 , wherein the barrier layer has a thickness under the gate electrode, wherein the thickness ranges from about 5 nm to about 15 nm.

10. The semiconductor device of claim 1 , further comprising a buffer layer between the substrate and the channel layer.

11. The semiconductor device of claim 1 , wherein the upper portion and the lower portion of the compound semiconductor layer have different dopant concentrations.

12. A method for fabricating the semiconductor device as set forth in claim 1 , comprising:
forming a channel layer on a substrate;
forming a barrier layer on the channel layer;
forming a nitride layer on the barrier layer;
recessing the nitride layer and the barrier layer to form a recess, wherein the recess penetrates through the nitride layer and a portion of the barrier layer;
conformally forming a spacer layer on the nitride layer and in the recess;
forming a compound semiconductor layer on the spacer layer, wherein the compound semiconductor layer comprises an upper portion and a lower portion, wherein the lower portion of the compound semiconductor layer fills the recess;
forming a gate electrode on the compound semiconductor layer; and
forming a pair of source/drain electrodes on opposite sides of the gate electrode, wherein the pair of source/drain electrodes extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.

13. The method for fabricating a semiconductor device of claim 12 , wherein the nitride layer comprises gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN), or a combination thereof.

14. The method for fabricating a semiconductor device of claim 12 , wherein a thickness of the nitride layer ranges from about 1 nm to about 20 nm.

15. The method for fabricating a semiconductor device of claim 12 , wherein a bandgap of the nitride layer is larger than a bandgap of the compound semiconductor layer and a bandgap of the spacer layer.

16. The method for fabricating a semiconductor device of claim 15 , wherein the spacer layer comprises aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlGaInN), or a combination thereof.

17. The method for fabricating a semiconductor device of claim 12 , wherein a thickness of the spacer layer ranges from about 1 nm to about 7 nm.

18. The method for fabricating a semiconductor device of claim 12 , wherein the pair of source/drain electrodes penetrates through the barrier layer and extends to the channel layer.

19. The method for fabricating a semiconductor device of claim 12 , wherein the barrier layer has a maximum thickness, wherein the maximum thickness ranges from about 10 nm to about 60 nm.

20. The method for fabricating a semiconductor device of claim 19 , wherein the barrier layer has a thickness under the gate electrode, wherein the thickness ranges from about 5 nm to about 15 nm.

21. The method for fabricating a semiconductor device of claim 12 , further comprising a buffer layer between the substrate and the channel layer.

22. The method for fabricating a semiconductor device of claim 12 , wherein the upper portion and the lower portion of the compound semiconductor layer have different dopant concentrations.

23. The semiconductor device of claim 1 , wherein the barrier layer has a reduced thickness directly under the lower portion of the compound semiconductor layer.

Assignees

• Vanguard Int Semiconduct Corp

Inventors

• Chen Chih-Yen
• Hung Chang-Xiang

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title