Semiconductor device, high electron mobility transistor (HEMT) and method of manufacturing

Patent metadata

Field	Value
Publication number	US-9245991-B2
Application number	US-201313964530-A
Country	US
Kind code	B2
Filing date	Aug 12, 2013
Priority date	Aug 12, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a channel layer over the substrate;
an active layer over the channel layer, the active layer configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; and
a barrier structure between the substrate and the channel layer, the barrier structure configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.

2. The semiconductor device of claim 1 , further comprising:
a buffer layer between the substrate and the channel layer, the buffer layer having a higher resistivity than a resistivity of the channel layer.

3. The semiconductor device of claim 2 , wherein the barrier structure comprises a first barrier layer between the substrate and the buffer layer, the first barrier layer configured to block diffusion of the material of the substrate to the buffer layer.

4. The semiconductor device of claim 3 , wherein the barrier structure comprises a second barrier layer between the buffer layer and the channel layer, the second barrier layer configured to block diffusion of the dopant from the buffer layer to the channel layer.

5. The semiconductor device of claim 4 , wherein at least one of the first barrier layer or the second barrier layer comprises at least one material selected from the group consisting of SiC, SiCN x and BN.

6. The semiconductor device of claim 2 , wherein the dopant comprises a p-type dopant.

7. The semiconductor device of claim 6 , wherein the p-type dopant comprises at least one element selected from the group consisting of C, Fe, Mg and Zn.

8. The semiconductor device of claim 6 , wherein the channel layer comprises the p-type dopant at a concentration lower than a concentration of the p-type dopant in the buffer layer.

9. The semiconductor device of claim 2 , wherein the barrier structure comprises a barrier layer between the buffer layer and the channel layer, the barrier layer configured to block diffusion of the dopant from the buffer layer to the channel layer.

10. The semiconductor device of claim 9 , wherein the barrier layer comprises at least one material selected from the group consisting of SiC, SiCN x and BN.

11. A High Electron Mobility Transistor (HEMT), comprising:
a Si substrate;
a first barrier layer over the Si substrate, the first barrier layer comprising at least one material selected from the group consisting of SiC, SiCN x and BN;
a buffer layer over the first barrier layer, the buffer layer comprising GaN doped with a p-type dopant;
a second barrier layer over the buffer layer, the second barrier layer comprising at least one material selected from the group consisting of SiC, SiCN x and BN;
a channel layer over the second barrier layer, the channel layer comprising GaN; and
an active layer over the channel layer, the active layer comprising Al y Ga (1-y) N.

12. The HEMT of claim 11 , wherein the p-type dopant comprises at least one element selected from the group consisting of C, Fe, Mg and Zn.

13. The HEMT of claim 11 , wherein the channel layer comprises the p-type dopant at a concentration lower than a concentration of the p-type dopant in the buffer layer.

14. The HEMT of claim 11 , further comprising:
an AlN layer over the Si substrate; and
a plurality of AlGaN layers over the AlN layer and under the first barrier layer, the plurality of AlGaN layers having an Al concentration reducing toward the first barrier layer.

15. The HEMT of claim 11 , wherein each of the first and second barrier layers has a thickness of 10 to 200 nm.

16. A High Electron Mobility Transistor (HEMT), comprising:
a substrate;
a buffer layer over the substrate, the buffer layer comprising GaN;
a first barrier layer between the substrate and the buffer layer, the first barrier layer configured to block diffusion of the material of the substrate or a first dopant;
a channel layer over the buffer layer, the channel layer comprising GaN;
a second barrier layer between the buffer layer and the channel layer, the second barrier layer configured to block diffusion of a material of the buffer layer or a second dopant;
an active layer over the channel layer, the active layer comprising Al y Ga (1-y) N.

17. The HEMT of claim 16 , wherein each of the first barrier layer and the second barrier layer independently comprises at least one material selected from the group consisting of SiC, SiCN x , and BN.

18. The HEMT of claim 16 , wherein each of the first barrier layer and the second barrier layer independently has a thickness of 10 nanometers (nm) to 200 nm.

19. The HEMT of claim 16 , wherein the active layer has a thickness ranging from 10 nm to 40 nm.

20. The HEMT of claim 16 , wherein the channel layer has a thickness of 200 nm to 500 nm.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liu Po-Chun
• Chen Chi-Ming
• Chiang Chen-Hao
• Yu Chung-Yi
• Tsai Chia-Shiung
• Chen Xiaomeng

Classifications

• H10P14/2908

  Nitrides · CPC title

• H10P14/2904

  Silicon carbide · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/854

  further characterised by the dopants · CPC title

• H10D62/82

  Heterojunctions · CPC title