Gate all around device

Patent metadata

Field	Value
Publication number	US-12094946-B2
Application number	US-202217718080-A
Country	US
Kind code	B2
Filing date	Apr 11, 2022
Priority date	Sep 28, 2017
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A device includes a nanostructure, a gate dielectric layer, a gate electrode, and a gate contact. The nanostructure is over a substrate. The gate dielectric layer laterally surrounds the nanostructure. The gate electrode laterally surrounds the gate dielectric layer. The gate electrode has a bottom surface and a top surface both higher than a bottom end of the nanostructure. The gate electrode has a horizontal dimension decreasing from the bottom surface to the top surface. The gate contact is electrically coupled to the gate electrode.

First claim

What is claimed is:

1. A device comprising:
a nanostructure over a substrate;
a gate dielectric layer laterally surrounding the nanostructure;
a gate electrode laterally surrounding the gate dielectric layer, the gate electrode having a bottom surface and a top surface both higher than a bottom end of the nanostructure, and the gate electrode having a horizontal dimension decreasing from the bottom surface to the top surface, wherein the gate electrode has a slanted sidewall slanted relative to an interface formed by the gate dielectric layer and the nanostructure; and
a gate contact electrically coupled to the gate electrode.

2. The device of claim 1 , wherein the gate contact has a rounded profile at a top region of the gate contact.

3. The device of claim 1 , further comprising:
a first source/drain contact electrically coupled to a first source/drain region of the nanostructure, the first source/drain contact having a rounded cross-sectional profile at a top region of the first source/drain contact.

4. The device of claim 3 , further comprising:
a second source/drain contact electrically coupled to a second source/drain region of the nanostructure, the second source/drain contact having a cross-sectional profile different from the rounded cross-sectional profile of the first source/drain contact.

5. The device of claim 1 , wherein the nanostructure and the gate electrode form a junctionless transistor.

6. The device of claim 1 , wherein the nanostructure is a doped metal.

7. The device of claim 1 , wherein the nanostructure comprises CoB, CoP, WB, WB or In 2 O 3 .

8. The device of claim 1 , wherein the gate electrode comprises polysilicon.

9. The device of claim 1 , further comprising:
a source/drain pickup metal layer over a substrate, the source/drain pickup metal layer having a bottom surface, a top surface, and a horizontal dimension decreasing from the bottom surface to the top surface, the bottom end of the nanostructure being in contact with the source/drain pickup metal layer.

10. A device comprising:
a source/drain pickup metal layer over a substrate, the source/drain pickup metal layer having a bottom surface, a top surface, and a horizontal dimension decreasing from the bottom surface to the top surface;
a nanostructure over the source/drain pickup metal layer, the nanostructure comprising a first source/drain region on the top surface of the source/drain pickup metal layer, a second source/drain region above the first source/drain region, and a horizontal dimension smaller than the horizontal dimension of the top surface of the source/drain pickup metal layer;
a gate dielectric layer laterally surrounding the nanostructure; and
a gate electrode laterally surrounding the gate dielectric layer.

11. The device of claim 10 , wherein the nanostructure further comprises a channel region between the first source/drain region and the second source/drain region, and the channel region has a same dopant as the first source/drain region and the second source/drain region.

12. The device of claim 11 , wherein the channel region has a different dopant concentration than the first source/drain region and the second source/drain region.

13. The device of claim 10 , further comprising:
a source/drain contact on a top surface of the source/drain pickup metal layer.

14. The device of claim 10 , further comprising:
a source/drain contact on an inclined sidewall of the source/drain pickup metal layer.

15. The device of claim 10 , wherein the gate electrode has a horizontal dimension decreasing as a distance from the source/drain pickup metal layer increases.

16. A device comprising:
a gate electrode having a trapezoidal cross-sectional pattern;
a channel structure extending from an upper base of the trapezoidal cross-sectional pattern of the gate electrode to below a lower base of the trapezoidal cross-sectional pattern of the gate electrode, wherein the lower base of the trapezoidal cross-sectional pattern of the gate electrode is wider than the upper base of the trapezoidal cross-sectional pattern of the gate electrode; and
a gate dielectric spacing the channel structure apart from the gate electrode.

17. The device of claim 16 , wherein the gate dielectric has a bottom below the lower base of the trapezoidal cross-sectional pattern of the gate electrode.

18. The device of claim 16 , wherein the gate dielectric has a top level with the upper base of the trapezoidal cross-sectional pattern of the gate electrode.

19. The device of claim 16 , further comprising:
a gate pickup metal layer below the lower base of the trapezoidal cross-sectional pattern of the gate electrode, the gate pickup metal layer having a horizontal dimension greater than a horizontal dimension of the lower base of the trapezoidal cross-sectional pattern of the gate electrode.

20. The device of claim 19 , further comprising:
a source/drain pickup metal layer below the gate pickup metal layer, the source/drain pickup metal layer having a maximal horizontal dimension greater than the horizontal dimension of the gate pickup metal layer; and
a dielectric layer interposing the source/drain pickup metal layer and the gate pickup metal layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Yung-Chih
• Liao Yu-Chieh
• Yang Tai-I
• Chen Hsin-Ping

Classifications

• H10D62/122

  oriented at angles to substrates, e.g. perpendicular to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6728

  Vertical TFTs · CPC title