Fast search for leaky word line

Patent metadata

Field	Value
Publication number	US-12094550-B2
Application number	US-202217886163-A
Country	US
Kind code	B2
Filing date	Aug 11, 2022
Priority date	Aug 11, 2022
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

Technology is disclosed herein for detecting leaky word lines in a non-volatile storage system. The exact leaky word line may be located very rapidly using a divide and conquer approach. First a determination may be made whether at least one word line in a group such as any of the word lines in a block is leaky. This initial determination can be made very quickly. If no word line in the group is leaky, the search can end. However, responsive to a determination that at least one word line in the group is leaky, a divide and conquer search may be performed in which the group of the word lines is repeatedly divided into smaller sub-groups with selected smaller sub-groups tested for a short circuit until the leaky word line is located.

First claim

What is claimed is:

1. An apparatus comprising:
a memory structure comprising non-volatile memory cells; and
one or more control circuits in communication with the memory structure, wherein the one or more control circuits are configured to:
determine whether at least one word line in a group of word lines is involved in a short circuit; and
responsive to a determination that at least one word line in the group is involved in a short circuit, repeatedly divide the group into smaller sub-groups of the word lines and test selected smaller sub-groups for a short circuit until a word line involved in the short circuit is located.

2. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
repeatedly divide parent sub-groups of the word lines into multiple child sub-groups, wherein each word line in each respective parent sub-group is in one of the child sub-groups of the respective parent sub-group; and
select a child sub-group for testing for a short circuit responsive to a determination that the respective parent of the child contains at least one word line involved in a short circuit.

3. The apparatus of claim 2 , wherein:
the memory structure comprises multi-tier blocks each having an upper tier and a lower tier;
the group of word lines comprises all data word lines in a selected block;
a first child sub-group of the group of word lines comprises all data word lines in the upper tier in the selected block; and
a second child sub-group of the group of word lines comprises all data word lines in the lower tier in the selected block.

4. The apparatus of claim 3 , wherein:
the first child sub-group comprises a plurality of child sub-groups in the upper tier; and
the second child sub-group comprises a plurality of child sub-groups in the lower tier.

5. The apparatus of claim 4 , wherein:
each of the plurality of child sub-groups in the upper tier comprises child sub-groups each having a single word line; and
each of the plurality of child sub-groups in the lower tier comprises child sub-groups each having a single word line.

6. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
apply a first voltage to all of the word lines in the group;
apply a second voltage to a region of the memory structure, wherein the first voltage has a higher magnitude than the second voltage; and
determine whether a leakage current results from the first voltage and the second voltage to determine whether at least one word line in the group is involved in a short circuit;
responsive to a determination that there is at least one word line in the group involved in a short circuit, for each respective sub-group:
apply the first voltage to each word line in the respective smaller sub-group of the word lines;
apply the second voltage to the region of the memory structure;
apply a third voltage to all word lines in the group that are not in the respective sub-group, wherein the third voltage has a magnitude between the first voltage and the second voltage; and
determine whether a leakage current results from the first voltage and the second voltage to determine whether there is at least one word line in the respective smaller sub-group involved in a short circuit.

7. The apparatus of claim 6 , wherein:
the one or more control circuits are further configured to program the group using a program voltage applied to a selected word line and a boosting voltage applied to unselected word lines;
the first voltage has a magnitude at least as great as the program voltage; and
the third voltage has a magnitude of approximately the boosting voltage.

8. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
output a pass/fail status for each word line in the group, including output a fail status for the word line involved in the short circuit.

9. The apparatus of claim 8 , wherein the pass/fail status for each word line is a single bit.

10. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
receive a request for a pass/fail status for a specifically identified set of the word lines in the group; and
output a pass/fail status for each word line in the specifically identified set responsive to the request.

11. The apparatus of claim 1 , wherein the short circuit comprises a word line to memory hole short circuit.

12. The apparatus of claim 1 , wherein the short circuit comprises a word line to source line short circuit.

13. A method for locating a leaky word line in a memory structure comprising blocks having NAND strings, the method comprising:
applying a high voltage to all word lines in a selected block while applying a low voltage to another region memory structure, wherein the high voltage has a higher magnitude than the low voltage;
determining whether a leakage current results from applying the high voltage and the low voltage to determine whether there is a leaky word line in the selected block;
responsive to a determination that there is a leaky word line in the selected block, repeatedly dividing the selected block of the word lines into smaller sub-groups and testing selected smaller sub-groups until the leaky word line is located including for each respective sub-group:
applying the high voltage to each word line in the respective sub-group while applying the low voltage to the other region memory structure;
applying a medium voltage to all word lines in the group that are not in the respective sub-group, wherein the medium voltage has a magnitude between the high voltage and the low voltage; and
determining whether a leakage current results from the high voltage and the low voltage to determine whether there is a leaky word line in the respective sub-group.

14. The method of claim 13 , wherein the other region of the memory structure comprises a source line connected to a source end of the NAND strings in the selected block and bit lines connected to respective drain ends of the NAND strings in the selected block.

15. A non-volatile storage system, the system comprising:
a three-dimensional memory structure comprising blocks having word lines and NAND strings associated with the word lines;
means for determining whether a selected block has a leaky word line; and
means for searching for the leaky word line in a series of steps in which for each step only word lines that are still potentially the leaky word line are divided into multiple smaller test groups until the leaky word line is located.

16. The non-volatile storage system of claim 15 , wherein:
each block includes an upper tier having upper tier word lines and a lower tier having lower tier word lines; and
the means for searching for the leaky word line in a series of steps is further for searching the upper tier word lines for the leaky word line and searching the lower tier word lines for the leaky word line.

17. The non-volatile storage system of claim 16 , wherein the means for searching for the leaky word line in a series of steps is further for:
searching only sub-groups of word lines in the lower tier responsive to a determination that the leaky word line is in the lower tier but is not in the upper tier; and
searching only sub-groups of word lines in the upper tier responsive to a determination that the leaky word line is in the upper tier but is not in the lower tier.

18. The non-volatile storage system of claim 15 , wherein the means for determining whether a selected block has a leaky word line

Assignees

• Western Digital Tech Inc
• Sandisk Technologies Inc

Inventors

• Zhou Xingyan
• Li Liang
• Qin Zhen
• Mak William
• Li Yan

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C2029/1202

  Word line control · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title