NAND boosting using dynamic ramping of word line voltages

Patent metadata

Field	Value
Publication number	US-10297329-B2
Application number	US-201615352390-A
Country	US
Kind code	B2
Filing date	Nov 15, 2016
Priority date	Nov 21, 2014
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.

First claim

What is claimed is:

1. An apparatus, comprising:
a set of memory cells; and
one or more control circuits configured to determine a programming waveform to be applied to a selected word line connected to a selected memory cell of the set of memory cells and determine a first voltage waveform to be applied to an unselected word line connected to an unselected memory cell of the set of memory cells, the programming waveform includes a voltage ramp to a programming voltage, the first voltage waveform includes a first initial ramp to a first initial voltage and a first final ramp to a pass voltage, the pass voltage is greater than the first initial voltage, the pass voltage is less than the programming voltage, the one or more control circuits configured to cause the programming voltage waveform to be applied to the selected word line and the first voltage waveform to be applied to the unselected word line during a programming operation such that the first final ramp to the pass voltage occurs after the selected word line has been set to the programming voltage, the one or more control circuits configured to cause the first voltage waveform to be applied to the unselected word line during the programming operation such that a continuous voltage ramping of the unselected word line occurs for the remainder of the programming operation after the selected word line has been set to the programming voltage.

2. The apparatus of claim 1 , wherein:
the one or more control circuits configured to determine a second voltage waveform to be applied to a second unselected word line connected to a second unselected memory cell of the set of memory cells, the second voltage waveform includes a second initial ramp to a second initial voltage and a second final ramp from the second initial voltage to the pass voltage, the one or more control circuits configured to cause the second voltage waveform to be applied to the second unselected word line during the programming operation such that the second final ramp to the pass voltage occurs after the selected word line has been set to the programming voltage.

3. The apparatus of claim 2 , wherein:
the one or more control circuits configured to cause the second voltage waveform to be applied to the second unselected word line during the programming operation such that the second final ramp to the pass voltage occurs after the unselected word line has been set to the pass voltage.

4. The apparatus of claim 2 , wherein:
the one or more control circuits configured to cause the second voltage waveform to be applied to the second unselected word line during the programming operation such that the second final ramp to the pass voltage occurs concurrent with the first final ramp to the pass voltage.

5. The apparatus of claim 2 , wherein:
the selected word line is adjacent to the second unselected word line; and
the unselected word line is adjacent to the second unselected word line.

6. The apparatus of claim 1 , wherein:
the first initial ramp to the first initial voltage is steeper than the first final ramp to the pass voltage.

7. The apparatus of claim 1 , wherein:
the voltage ramp to the programming voltage is steeper than the first final ramp to the pass voltage.

8. The apparatus of claim 2 , wherein:
the first final ramp to the pass voltage is steeper than the second final ramp to the pass voltage.

9. The apparatus of claim 1 , wherein:
the set of memory cells are part of a three-dimensional memory array.

10. The apparatus of claim 1 , wherein:
the set of memory cells comprise memory cell transistors in a NAND string.

11. A method, comprising:
determining a programming waveform to be applied to a selected word line connected to a selected memory cell transistor within a NAND string, the programming waveform includes a voltage ramp to a programming voltage;
determining a first voltage waveform to be applied to an unselected word line connected to an unselected memory cell transistor within the NAND string, the first voltage waveform includes a first initial ramp to a first initial voltage and a first final ramp to a pass voltage, the pass voltage is greater than the first initial voltage, the pass voltage is less than the programming voltage; and
applying the programming voltage waveform to the selected word line and the first voltage waveform to the unselected word line during a programming operation such that the first final ramp to the pass voltage occurs after the selected word line has reached the programming voltage, the applying the first voltage waveform to the unselected word line during the programming operation includes providing a continuous voltage ramping of the unselected word line after the selected word line has reached the programming voltage for the remainder of the programming operation.

12. The method of claim 11 , further comprising:
determining a second voltage waveform to be applied to a second unselected word line connected to a second unselected memory cell transistor of the NAND string, the second voltage waveform includes a second initial ramp to a second initial voltage and a second final ramp from the second initial voltage to the pass voltage; and
applying the second voltage waveform to the second unselected word line during the programming operation such that the second final ramp to the pass voltage occurs after the selected word line has reached the programming voltage.

13. The method of claim 12 , wherein:
the second voltage waveform is applied to the second unselected word line during the programming operation such that the second final ramp to the pass voltage occurs after the unselected word line has reached the pass voltage.

14. The method of claim 12 , wherein:
the second voltage waveform is applied to the second unselected word line during the programming operation such that the second final ramp to the pass voltage overlaps in time with the first final ramp to the pass voltage.

15. The method of claim 12 , wherein:
the selected word line is adjacent to the second unselected word line; and
the unselected word line is adjacent to the second unselected word line.

16. The method of claim 11 , wherein:
the voltage ramp to the programming voltage is steeper than the first final ramp to the pass voltage.

17. A system, comprising:
a string of memory cells including a selected memory cell and an unselected memory cell; and
one or more control circuits configured to apply a programming voltage waveform to the selected memory cell and a first voltage waveform to the unselected memory cell during a programming operation, the programming waveform includes a voltage ramp to a programming voltage, the first voltage waveform includes a first final ramp to a pass voltage less than the programming voltage, the one or more control circuits configured to apply the programming voltage waveform to the selected memory cell and the first voltage waveform to the unselected memory cell during the programming operation such that the first final ramp to the pass voltage occurs after the selected memory cell has been set to the programming voltage and a continuous voltage ramping of the unselected word line occurs for the remainder of the programming operation after the selected word line has been set to the programming voltage.

18. The system of claim 17 , wherein:
the voltage ramp to the programming voltage is steeper than the first final ramp to the pass voltage.

Assignees

• Sandisk Technologies Llc

Inventors

• Rabkin Peter
• Dong Yingda
• Higashitani Masaaki

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title