Detection and localization of failures in 3D NAND flash memory

Patent metadata

Field	Value
Publication number	US-9529663-B1
Application number	US-201514975784-A
Country	US
Kind code	B1
Filing date	Dec 20, 2015
Priority date	Dec 20, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A method includes, in a memory block, which includes at least a string of memory cells that is selectable using at least a select transistor, sensing a current flowing through the string. A failure in the memory block, which causes the string to conduct even when unselected using the select transistor, is detected based on the sensed current. A corrective action is initiated in response to the identified failure.

First claim

The invention claimed is:

1. An apparatus, comprising:
a memory, comprising multiple memory blocks, each memory block comprising multiple strings of memory cells, wherein each string is selectable using at least a respective select transistor; and
control circuitry, which is configured to sense a current flowing through a given string in a given memory block of the memory, to detect, based on the sensed current, a failure in the given memory block that causes the given string to conduct even when the given string is unselected using the respective select transistor, and to initiate a corrective action in response to the identified failure in the given memory block.

2. The apparatus according to claim 1 , wherein the select transistor comprises a source-select transistor (SGS) or a drain-select transistor (SGD).

3. The apparatus according to claim 1 , wherein the control circuitry is configured to sense the current following erasure of the given memory block.

4. The apparatus according to claim 1 , wherein the control circuitry is configured to perform an erase-verification operation during which a gate of the select transistor is set to a positive voltage, to perform a re-read operation in which the gate is set to zero voltage, and to detect the failure by comparing the current sensed during the erase-verification operation to the current sensed during the re-read operation.

5. The apparatus according to claim 4 , wherein the control circuitry is configured to detect the failure by detecting that the current sensed during the re-read operation is lower than the current sensed during the erase-verification operation by less than a predefined margin.

6. The apparatus according to claim 1 , wherein the control circuitry comprises a programming-and-verification (P&V) circuit for verifying programming of the memory cells with data, and wherein the control circuitry is configured to sense the current using the P&V circuit.

7. The apparatus according to claim 6 , wherein the corrective action comprises programming of at least some of the memory cells in the given memory block to a positive threshold voltage.

8. The apparatus according to claim 7 , wherein the control circuitry is configured to program the memory cells by applying to each of the memory cells a single programming pulse.

9. The apparatus according to claim 7 , wherein the control circuitry is configured to notify a memory controller or host of the failure, and to receive from the memory controller or host an instruction to program the memory cells.

10. A method, comprising:
in a memory, which comprises multiple memory blocks, each memory block comprising multiple strings of memory cells, wherein each string is selectable using at least a respective select transistor, sensing a current flowing through a given string in a given memory block of the memory;
based on the sensed current, detecting a failure in the given memory block that causes the given string to conduct even when the given string is unselected using the respective select transistor; and
initiating a corrective action in response to the identified failure in the given memory block.

11. The method according to claim 10 , wherein the select transistor comprises a source-select transistor (SGS) or a drain-select transistor (SGD).

12. The method according to claim 10 , wherein sensing the current comprises assessing the current following erasure of the given memory block.

13. The method according to claim 10 , wherein sensing the current comprises performing an erase-verification operation during which a gate of the select transistor is set to a positive voltage, and performing a re-read operation in which the gate is set to zero voltage, and wherein detecting the failure comprises comparing the current sensed during the erase-verification operation to the current sensed during the re-read operation.

14. The method according to claim 13 , wherein detecting the failure comprises detecting that the current sensed during the re-read operation is lower than the current sensed during the erase-verification operation by less than a predefined margin.

15. The method according to claim 10 , wherein sensing the current comprises assessing the current using a programming-and-verification (P&V) circuit that is also used for verifying programming of the memory cells with data.

16. The method according to claim 10 , wherein initiating the corrective action comprises initiating programming of at least some of the memory cells in the given memory block to a positive threshold voltage.

17. The method according to claim 16 , wherein programming of the memory cells comprises applying to each of the memory cells a single programming pulse.

18. The method according to claim 16 , wherein initiating the programming comprises notifying a memory controller or host of the failure, and receiving from the memory controller or host an instruction to program the memory cells.

Assignees

• Apple Inc

Inventors

• Srinivasan Charan
• Gurgi Eyal

Classifications

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title