Non-volatile memory with multi-word line select for defect detection operations

Patent metadata

Field	Value
Publication number	US-9449694-B2
Application number	US-201414477339-A
Country	US
Kind code	B2
Filing date	Sep 4, 2014
Priority date	Sep 4, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.

First claim

It is claimed:

1. A non-volatile memory circuit, comprising:
an array of non-volatile memory cells fainted according to a NAND architecture as a plurality of blocks, each block formed of a plurality of NAND strings having multiple memory cells connected in series and connected along word lines;
bias circuitry providing bias voltage levels for use in the operation of the array; and
decoding circuitry whereby the bias circuit is connectable to the array to selectively apply the bias voltage levels thereto,
wherein, when performing a programming operation on a selected word line, the decoding circuitry applies a programming voltage to the selected word line while applying a pass voltage to the other word lines of the block to which the selected word line belongs, the programming voltage being higher that the pass voltage, and
wherein, when performing a multi-word line stress operation on a first plurality of selected word lines of a first block in which the first plurality of selected word lines are a contiguous group of word lines of the first block, the decoding circuitry applies a stress voltage concurrently to the first plurality of selected word lines while applying the pass voltage to non-selected word lines of the first block, the stress voltage being higher than the pass voltage.

2. The non-volatile memory circuit of claim 1 , wherein the bias circuitry includes a charge pump that generates the programming voltage.

3. The non-volatile memory circuit of claim 1 , wherein the bias circuitry includes a charge pump that generates the stress voltage.

4. The non-volatile memory circuit of claim 1 , wherein the bias circuitry includes a charge pump that generates the pass voltage.

5. The non-volatile memory circuit of claim 1 , wherein the stress voltage is the programming voltage.

6. The non-volatile memory circuit of claim 1 , wherein the stress voltage is higher than the programming voltage.

7. The non-volatile memory circuit of claim 1 , wherein the non-selected word lines of the first block to which the pass voltage is applied for the multi-word line stress operation are all of the non-selected word lines of the first block.

8. The non-volatile memory circuit of claim 1 , wherein the first plurality of selected word lines includes an edge word line of the selected block.

9. The non-volatile memory circuit of claim 1 , wherein the first plurality of selected word lines does not include an edge word line of the selected block.

10. The non-volatile memory circuit of claim 1 , wherein the non-volatile memory circuit performs the stress operation as part of a built in self-test operation.

11. The non-volatile memory circuit of claim 1 , wherein the non-volatile memory circuit performs the stress operation in response to an external command.

12. The non-volatile memory circuit of claim 1 , wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

13. The non-volatile memory circuit of claim 12 , wherein the NAND strings run in a vertical direction relative to the substrate, and the word lines run in a horizontal direction relative to the substrate.

14. The non-volatile memory circuit of claim 1 , wherein the non-volatile memory circuit is a monolithic two-dimensional semiconductor memory device where the memory cells are arranged in a single physical level.

15. The non-volatile memory circuit of claim 1 , wherein the first plurality of selected word lines of the first block is all of the word lines of the first block.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Paudel Rajan
• Sabde Jagdish
• Magia Sagar
• Nguyen Khanh

Classifications

• G11C2029/2602

  Concurrent test · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C29/26

  Accessing multiple arrays (G11C29/24 takes precedence) · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title