Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block

Patent metadata

Field	Value
Publication number	US-9330783-B1
Application number	US-201414572818-A
Country	US
Kind code	B1
Filing date	Dec 17, 2014
Priority date	Dec 17, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.

First claim

The invention claimed is:

1. An apparatus, comprising:
a memory, comprising a memory block that comprises memory cells connected by word lines; and
a memory controller configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block, while the memory and the memory controller are operating in a host system, by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.

2. The apparatus according to claim 1 , wherein the suspected short-circuit event comprises at least one of a short-circuit between two of the word lines and a short-circuit between a word line and a substrate of the memory block.

3. The apparatus according to claim 1 , wherein the memory controller is configured to recognize the deviation by detecting an imbalance between counts of respective data values in the data read from the memory cells of at least the given word line, relative to the remaining word lines.

4. The apparatus according to claim 1 , wherein the memory controller is configured to recognize the deviation in a threshold voltage distribution of the memory cells of at least the given word line, relative to the remaining word lines.

5. The apparatus according to claim 1 , wherein the memory controller is configured to recognize the deviation in a programming or erasure voltage of at least the given word line, relative to the remaining word lines.

6. The apparatus according to claim 1 , wherein the memory controller is configured to recognize the deviation in a programming or erasure duration of at least the given word line, relative to the remaining word lines.

7. The apparatus according to claim 1 , wherein the memory controller is configured to recognize the deviation by detecting in at least the given word line at least one erased memory cell whose threshold voltage has become positive.

8. The apparatus according to claim 7 , wherein the memory controller is configured to recognize the deviation by detecting that a count of erased memory cells whose threshold voltage has become positive progressively decreases in successive word lines starting from the given word line.

9. The apparatus according to claim 1 , wherein the memory controller is configured to recognize the deviation in an electrical resistance between at least the given word line and a substrate of the memory block, relative to the remaining word lines.

10. The apparatus according to claim 1 , wherein the memory controller is configured to detect that the suspected short-circuit event is between a substrate of the memory block and at least one of the word lines subsequent to the given word line in the memory block.

11. The apparatus according to claim 1 , wherein the memory comprises one or more sensors for sensing voltage on at least one of the word lines, and wherein the memory controller is configured to identify the suspected short-circuit event based on the sensed voltage.

12. An apparatus, comprising:
a memory, comprising a memory block that comprises memory cells connected by word lines; and
a memory controller configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation in a number of readout errors in the data read from the memory cells of at least the given word line, relative to remaining word lines in the memory block.

13. A method, comprising:
storing data in a memory that comprises a memory block comprising memory cells connected by word lines; and
using a memory controller, identifying a suspected short-circuit event in the memory block, while the memory and the memory controller are operating in a host system, by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.

14. The method according to claim 13 , wherein identifying the suspected short-circuit event comprises identifying at least one of a short-circuit between two of the word lines and a short-circuit between a word line and a substrate of the memory block.

15. The method according to claim 13 , wherein identifying the suspected short-circuit event comprises recognizing the deviation in a number of readout errors in the data read from the memory cells of at least the given word line, relative to the remaining word lines.

16. The method according to claim 13 , wherein identifying the suspected short-circuit event comprises recognizing the deviation in a programming or erasure voltage of at least the given word line, relative to the remaining word lines.

17. The method according to claim 13 , wherein identifying the suspected short-circuit event comprises recognizing the deviation in a programming or erasure duration of at least the given word line, relative to the remaining word lines.

18. The method according to claim 13 , wherein identifying the suspected short-circuit event comprises recognizing the deviation by detecting in at least the given word line at least one erased memory cell whose threshold voltage has become positive.

19. The method according to claim 13 , wherein identifying the suspected short-circuit event comprises detecting that the suspected short-circuit event is between a substrate of the memory block and at least one of the word lines subsequent to the given word line in the memory block.

Assignees

• Apple Inc

Inventors

• Rotbard Barak
• Meir Avraham Poza
• Gurgi Eyal
• Shur Yael
• Baum Barak

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C29/02 Primary

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/006

  at wafer scale level, i.e. wafer scale integration [WSI] · CPC title

• G11C29/025 Primary

  in signal lines · CPC title