Package core assembly and fabrication methods

Patent metadata

Field	Value
Publication number	US-12087679-B2
Application number	US-202016886704-A
Country	US
Kind code	B2
Filing date	May 28, 2020
Priority date	Nov 27, 2019
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

First claim

What is claimed is:

1. A semiconductor device assembly, comprising:
a silicon core structure comprising:
a first side opposing a second side;
at least one via, the at least one via comprising a via surface extending between the first side and the second side; and
a metal cladding layer formed on and in direct contact with the first side, the second side, and the via surface, the metal cladding layer extending along the via surface between the first side and the second side;

a dielectric layer formed over the metal cladding layer on the first side, the second side, and the via surface, the dielectric layer extending along the metal cladding layer between the first side and the second side;
a conductive interconnection formed through the at least one via of the silicon core structure and having a surface exposed at the first side and the second side;
a first redistribution layer formed over the first side; and
a second redistribution layer formed over the second side, wherein the first redistribution layer and the second redistribution layer each have one or more conductive contacts formed thereon, and wherein the metal cladding layer is conductively coupled to ground or a reference voltage by at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer, wherein the metal cladding layer has a thickness between about 100 nm and about 5 μm on substantially all exposed surfaces of the silicon core.

2. The semiconductor device assembly of claim 1 , wherein the metal cladding layer comprises nickel.

3. The semiconductor device assembly of claim 1 , wherein the metal cladding layer circumferentially surrounds the one or more conductive interconnections formed through the silicon core structure.

4. The semiconductor device assembly of claim 3 , wherein the metal cladding layer is conductively coupled to ground by at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer.

5. The semiconductor device assembly of claim 3 , wherein the metal cladding layer is conductively coupled to a reference voltage by at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer.

6. The semiconductor device assembly of claim 1 , wherein the dielectric layer comprises a flowable epoxy resin material.

7. A semiconductor device comprising:
a silicon core structure comprising:
a first side opposing a second side;
at least one via, the at least one via comprising a via surface extending between the first side and the second side; and
a metal cladding layer formed on and in direct contact with the first side, the second side, and the via surface, the metal cladding layer extending along the via surface between the first side and the second side;

a dielectric layer formed over the metal cladding layer on the first side, the second side, and the via surface, the dielectric layer extending along the metal cladding layer between the first side and the second side;
a conductive interconnection formed through the at least one via of the silicon core structure and having a surface exposed at the first side and the second side;
a first redistribution layer formed over the first side; and
a second redistribution layer formed over the second side, wherein the first redistribution layer and the second redistribution layer each have one or more conductive contacts formed thereon, and wherein the metal cladding layer is conductively coupled to ground or a reference voltage by at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer, wherein the dielectric layer comprises a flowable epoxy resin material comprising silica particles ranging in size between about 80 nm and about 1 μm.

8. The semiconductor device assembly of claim 7 , wherein the dielectric layer has a thickness of between about 5 μm and about 50 μm.

9. A semiconductor device assembly, comprising:
a silicon core structure having a first side opposing a second side;
a via formed through the silicon core structure and comprising a via surface extending between the first side and the second side;
a nickel cladding layer formed on and in direct contact with the first side, the second side, and the via surface, the nickel cladding layer extending along the via surface between the first side and the second side;
a dielectric layer formed over the nickel cladding layer on the first side, the second side, and the via surface, the dielectric layer extending along the nickel cladding layer between the first side and the second side, the dielectric layer comprising an epoxy resin;
a conductive interconnection formed through the via and having a surface exposed at the first side and the second side; and
a redistribution layer formed on the dielectric layer, the redistribution layer comprising:
an adhesion layer formed on the dielectric layer, the adhesion layer comprising molybdenum;
a copper seed layer formed on the adhesion layer; and
a copper layer formed on the copper seed layer, wherein the nickel cladding layer is conductively coupled to ground or a reference voltage by a conductive cladding connection through at least the dielectric layer.

Assignees

• Applied Materials Inc

Inventors

• Chen Han-Wen
• Verhaverbeke Steven
• Park Giback
• Cho Kyuil
• Leschkies Kurtis
• Gouk Roman
• Buch Chintan
• Dicaprio Vincent
• Stonas Bernhard
• Delmas Jean

Classifications

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/635 Primary

  Through-vias · CPC title

• H10W70/095 Primary

  of vias therein · CPC title

• H10W70/66

  Conductive materials thereof · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title