Device, method and system to predict an address collision by a load and a store

Patent metadata

Field	Value
Publication number	US-12086591-B2
Application number	US-202117214698-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Mar 26, 2021
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

Techniques and mechanisms for determining a relative order in which a load instruction and a store instruction are to be executed. In an embodiment, a processor detects an address collision event wherein two instructions, corresponding to different respective instruction pointer values, target the same memory address. Based on the address collision event, the processor identifies respective instruction types of the two instructions as an aliasing instruction type pair. The processor further determines a count of decisions each to forego a reversal of an order of execution of instructions. Each decision represented in the count is based on instructions which are each of a different respective instruction type of the aliasing instruction type pair. In another embodiment, the processor determines, based on the count of decisions, whether a later load instruction is to be advanced in an order of instruction execution.

First claim

What is claimed is:

1. A processor comprising:
manager circuitry to:
detect an address collision event wherein a memory address is targeted by both a first load instruction of a first instruction type and a first store instruction of a second instruction type, wherein the first instruction type and the second instruction type correspond to different respective instruction pointer values; and
determine, based on the address collision event, a count of decisions each to forego a reversal of an order of execution of a respective instruction of the first instruction type and a respective instruction of the second instruction type;

classification circuitry to perform an evaluation of the count based on a threshold maximum count value; and
prediction circuitry, coupled to the classification circuitry, to generate, based on the evaluation, a signal to determine an order of execution of a second load instruction of the first instruction type and a second store instruction of the second instruction type.

2. The processor of claim 1 , wherein the first instruction type is to correspond to a first instruction pointer value, and the second instruction type is to correspond to a second instruction pointer value, and wherein:
the manager circuitry is further to provide reference information, based on the address collision event, to indicate an assignment of a color to both the first instruction type and the second instruction type;
the classification circuitry is further to:
identify the first instruction type and the second instruction type based on the second load instruction and the second store instruction, respectively; and
access the reference information, based on the first instruction type and the second instruction type, to detect the assignment.

3. The processor of claim 2 , wherein the classification circuitry is further to:
tag the second load instruction, based on the assignment and the evaluation, with one of a first color or a second color to generate a first tagged instruction; and
tag the second store instruction with the first color, based on the assignment, to generate a second tagged instruction.

4. The processor of claim 3 , further comprising:
counter circuitry to maintain a count of good bypass prevention decisions which are each based on a respective instruction of the first instruction type;

wherein the prediction circuitry is to determine, based on the one of the first color or the second color, whether the order of execution of the second load instruction and the second store instruction is to be independent of the count of good bypass prevention decisions.

5. The processor of claim 1 , wherein the manager circuitry is to:
increment the count based on an instance of two instructions, each of a different respective one of the first instruction type or the second instruction type, which target different respective memory addresses; and
reset the count to a baseline value based on an instance of two other instructions, each of a different respective one of the first instruction type or the second instruction type, which target a same memory address.

6. The processor of claim 1 , wherein the classification circuitry is further to:
provide a tagged load instruction to a load buffer;
provide a tagged store instruction to a store buffer;

wherein the prediction circuitry is to:
determine that a first tagged instruction at the load buffer comprises a third load instruction and a first tag;
determine that a first tagged instruction at the store buffer comprises a third store instruction and a second tag;

wherein:
where neither the first tag nor the second tag is equal to a color, and the first tag is equal to the second tag, the processor is to execute the third load instruction after the third store instruction; and
where neither the first tag nor the second tag is equal to the color, and the first tag is not equal to the second tag, the processor is to execute the third load instruction before the third store instruction.

7. The processor of claim 6 , wherein, where the third load instruction is of a third instruction type, and where the first tag or the second tag is equal to the color, the prediction circuitry is to determine an order of execution of the third load instruction and the third store instruction based on a count of good bypass prevention decisions which are each based on a respective instruction of a third instruction type.

8. A method at a processor, the method comprising:
detecting that a memory address is targeted by both a first load instruction of a first instruction type and a first store instruction of a second instruction type, wherein the first instruction type and the second instruction type correspond to different respective instruction pointer values;
based on the detecting, determining a count of decisions each to forego a reversal of an order of execution of a respective instruction of the first instruction type and a respective instruction of the second instruction type;
performing an evaluation of the count based on a threshold maximum count value; and
based on the evaluation, generating a signal to determine an order of execution of a second load instruction of the first instruction type and a second store instruction of the second instruction type.

9. The method of claim 8 , wherein the first instruction type corresponds to a first instruction pointer value, and the second instruction type corresponds to a second instruction pointer value, the method further comprising:
based on the detecting, providing reference information to indicate an assignment of a color to both the first instruction type and the second instruction type;
identifying the first instruction type and the second instruction type based on the second load instruction and the second store instruction, respectively; and
based on the identifying, accessing the reference information to detect the assignment.

10. The method of claim 9 , further comprising:
based on the assignment and the evaluation, tagging the second load instruction with one of a first color or a second color to generate a first tagged instruction; and
based on the assignment, tagging the second store instruction with the first color to generate a second tagged instruction.

11. The method of claim 10 , further comprising:
maintaining a count of good bypass prevention decisions which are each based on a respective instruction of the first instruction type; and
determining, based on the one of the first color or the second color, whether the order of execution of the second load instruction and the second store instruction is to be independent of the count of good bypass prevention decisions.

12. The method of claim 8 , further comprising:
incrementing the count based on an instance of two instructions, each of a different respective one of the first instruction type or the second instruction type, targeting different respective memory addresses; and
resetting the count to a baseline value based on an instance of two other instructions, each of a different respective one of the first instruction type or the second instruction type, targeting a same memory address.

13. The method of claim 8 , further comprising:
providing a tagged load instruction to a load buffer;
providing a tagged store instruction to a store buffer;
determining that a first tagged instruction at the load buffer comprises a third load instruction and a first tag;
determining that a first tagged instruction at the store buffer comprises a third store instruction and a second tag;
where neither the first tag nor the second tag is equal to a col

Assignees

• Intel Corp

Inventors

• Shukla Sudhanshu
• Gaur Jayesh
• Shwartsman Stanislav
• Kryukov Pavel I

Classifications

• G06F9/3856

  Reordering of instructions, e.g. using queues or age tags · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title