Store address prediction for memory disambiguation in a processing device

Patent metadata

Field	Value
Publication number	US-9244827-B2
Application number	US-201314036591-A
Country	US
Kind code	B2
Filing date	Sep 25, 2013
Priority date	Sep 25, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A processing device implementing store address prediction for memory disambiguation in a processing device is disclosed. A processing device of the disclosure includes a store address predictor to predict an address for store operations that store data to a memory hierarchy. The processing device further includes a store buffer for buffering the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations. The processing device further includes a load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations.

First claim

What is claimed is:

1. A processing device, comprising:
a store address predictor to predict an address for store operations that store data to a memory hierarchy;
a store buffer communicably coupled to the store address predictor, the store buffer to buffer the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations; and
a load buffer communicably coupled to the store address predictor, the load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of a respective store operation and to determine whether to speculatively forward data from the respective store operation.

2. The processing device of claim 1 , wherein the store address predictor comprises a store address table comprising entries for the store operations, each entry comprising an index associated with an instruction point (IP) of an associated store operation of the store operations, the predicted address for the associated store operation, an entry state for the entry, and a counter value for the entry.

3. The processing device of claim 2 , wherein the store address table is a content addressable memory (CAM) array and the index is the IP of the associated store operation.

4. The processing device of claim 1 , wherein the store address predictor further comprises an address prediction component to generate the predicted addresses, wherein the address prediction component to generate the predicted addresses based on stride calculations of the store operations.

5. The processing device of claim 2 , wherein the store address predictor further comprises a threshold comparison component to determine, for each of the entries, whether the counter value exceeds a counter threshold has been reached by the counter value of the entry, wherein when the counter threshold has been reached, the address prediction component to set the entry state of the entry to suppress use of the predicted address by the store buffer.

6. The processing device of claim 1 , wherein the load buffer comprising an entry for the load operation that comprises a store buffer ID field to store a store buffer ID of an entry of the store buffer corresponding to a store operation from which the load operation speculatively forwarded data.

7. The processing device of claim 2 , wherein when a dispatched store operation of the store operations calculates a store address, and wherein the store buffer to:
overwrite the predicted address in the store buffer for the dispatched store operation with the calculated store address; and
verify whether the predicted address and the calculated address match.

8. The processing device of claim 7 , wherein when the predicted address and the calculated address do not match, the store address predictor to increment the counter value for the entry associated with the dispatched store operation.

9. The processing device of claim 6 , wherein the load operation is indicated as mispredicted when at least one of:
the load operation speculatively executes ahead of the dispatched store operation without speculatively forwarding data from the dispatched store operation and comprises an address that matches the calculated address;
the load operation speculatively forwarded the data from the dispatched store operation and the address of the load operation does not match the calculated address; or
the load operation speculatively forwarded data from another store operation of the store operations and the address of the load operation matches the calculated address.

10. A method, comprising:
predicting, by a store address predictor of a processing device, an address for store operations that stores data to a memory hierarchy;
allocating an entry in a store buffer for buffering the store operations prior to completion, the entry in the store buffer comprising the predicted address for each of the store operations; and
referencing, by a load operation of the processing device, the predicted address in the store buffer to determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations.

11. The method of claim 10 , wherein the store address predictor comprises a store address table comprising entries for the store operations, each entry comprising an index associated with an instruction point (IP) of an associated store operation of the store operations, the predicted address for the associated store operation, an entry state for the entry, and a counter value for the entry.

12. The method of claim 10 , wherein the store address predictor further comprises an address prediction component to generate the predicted addresses based on stride calculations of the store operations.

13. The method of claim 11 , wherein the store address predictor further comprises a threshold comparison component to determine, for each of the entries, whether the counter value exceeds a counter threshold has been reached by the counter value of the entry, and wherein when the counter threshold has been reached, setting, by the address prediction component, the entry state of the entry to suppress use of the predicted address by the store buffer.

14. The method of claim 10 , further comprising a load buffer for buffering the load operation, the load buffer comprising an entry for the load operation that comprises a store buffer ID field to store a store buffer ID of an entry of the store buffer corresponding to a store operation from which the load operation speculatively forwarded data.

15. The method of claim 14 , wherein when a dispatched store operation of the store operations calculates a store address:
overwriting the predicted address in the store buffer for the dispatched store operation with the calculated store address; and
verifying whether the predicted address and the calculated address match, wherein when the predicted address and the calculated address do not match, incrementing the counter value for the entry associated with the dispatched store operation.

16. A system comprising:
a memory hierarchy; and
a processing device communicably coupled to the memory hierarchy, the processing device comprising an execution unit comprising:
a store address predictor to predict an address for store operations that store data to the memory hierarchy;
a store buffer for buffering the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations; and
a load buffer communicably coupled to the store address predictor, the load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations.

17. The system of claim 16 , wherein the store address predictor comprises a store address table comprising entries for the store operations, each entry comprising an index associated with an instruction point (IP) of an associated store operation of the store operations, the predicted address for the associated store operation, an entry state for the entry, and a counter value for the entry.

18. The system of claim 16 , wherein the store address predictor further comprises an address prediction component to generate the predicted addresses based on stride calculations of the store operations.

Assignees

• Kim Ho-Seop
• Chappell Robert S
• Soo Choon Y
• Srinivasan Srikanth T
• Intel Corp

Inventors

• Kim Ho-Seop
• Chappell Robert S
• Soo Choon Y
• Srinivasan Srikanth T

Classifications

• G06F9/383 Primary

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F12/0215 Primary

  with look ahead addressing means · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/3832

  Value prediction for operands; operand history buffers · CPC title