Methods and Apparatus for Efficiently Processing Load Instruction Sequences
US-2026003626-A1 · Jan 1, 2026 · US
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Gaur Jayesh patents
Gaur Jayesh is listed as an inventor on 73 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Gaur Jayesh |
| Total patents | 73 |
| First publication | Mar 26, 2015 |
| Latest publication | Jan 1, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Device, method, and system to facilitate improved bandwidth of a branch prediction unit
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Bandwidth aware simultaneous multi-threading
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Software defined super cores
US-2025217160-A1 · Jul 3, 2025 · US
Early resteering of mispredicted branches
US-2025217155-A1 · Jul 3, 2025 · US
Software defined super cores
US-2025217157-A1 · Jul 3, 2025 · US
Register renaming caching
US-2025217288-A1 · Jul 3, 2025 · US
Apparatus and method for profile-optimized loops
US-2025199813-A1 · Jun 19, 2025 · US
Instruction and Micro-Architecture Support for Decompression on Core
US-2025117329-A1 · Apr 10, 2025 · US
Instruction and micro-architecture support for decompression on core
US-12182018-B2 · Dec 31, 2024 · US
Recent patents
Latest publications not already listed above.
Compressed cache memory with decompress on fault
US-12130738-B2 · Oct 29, 2024 · US
Device, method and system to predict an address collision by a load and a store
US-12086591-B2 · Sep 10, 2024 · US
Application programming interface for fine grained low latency decompression within processor core
US-12028094-B2 · Jul 2, 2024 · US
Apparatus and method for hardware-based memoization of function calls to reduce instruction execution
US-12020033-B2 · Jun 25, 2024 · US
Data relocation for inline metadata
US-11972126-B2 · Apr 30, 2024 · US
Instruction elimination through hardware driven memoization of loop instances
US-2024103874-A1 · Mar 28, 2024 · US
Short pipeline for fast recovery from a branch misprediction
US-2024103878-A1 · Mar 28, 2024 · US
Register File Prefetch
US-2023214325-A1 · Jul 6, 2023 · US
Device, method and system to provide a predicted value with a sequence of micro-operations
US-2023195465-A1 · Jun 22, 2023 · US
System, apparatus and method for throttling fusion of micro-operations in a processor
US-2023195456-A1 · Jun 22, 2023 · US
Device, method, and system to facilitate improved bandwidth of a branch prediction unit
US-2023195469-A1 · Jun 22, 2023 · US
Technology for dynamically tuning processor features
US-11656971-B2 · May 23, 2023 · US
Detecting a dynamic control flow re-convergence point for conditional branches in hardware
US-11645078-B2 · May 9, 2023 · US
Cryptographic computing engine for memory load and store units of a microarchitecture pipeline
US-11575504-B2 · Feb 7, 2023 · US
Device, method and system to predict an address collision by a load and a store
US-2022308876-A1 · Sep 29, 2022 · US
Technology For Dynamically Tuning Processor Features
US-2022206925-A1 · Jun 30, 2022 · US
Apparatus and method for hardware-based memoization of function calls to reduce instruction execution
US-2022206816-A1 · Jun 30, 2022 · US
Application programming interface for fine grained low latency decompression within processor core
US-2022197813-A1 · Jun 23, 2022 · US
Compressed cache memory with decompress on fault
US-2022197793-A1 · Jun 23, 2022 · US
Speculative decompression within processor core caches
US-2022197643-A1 · Jun 23, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 73 |
| Srinivasan Suresh | 1 |
| Ramesh Rakesh | 1 |
| Subramoney Sreenivas | 1 |
| Gaur Jayesh | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0811 | 23 |
| G06F12/0862 | 17 |
| G06F9/3836 | 17 |
| G06F2212/401 | 12 |
| G06F9/3806 | 12 |